Sherif M Goma

7276787, Oct 2, 2007

Dec 5, 2003

10/729254

Daniel Charles Edelstein - White Plains NY, US
Paul Stephen Andry - Mohegan Lake NY, US
Leena Paivikki Buchwalter - Hopewell Junction NY, US
Jon Alfred Casey - Poughkeepsie NY, US
Sherif A. Goma - Hawthorne NY, US
Raymond R. Horton - Dover Plains NY, US
Gareth Geoffrey Hougham - Ossining NY, US
Michael Wayne Lane - Cortlandt Manor NY, US
Xiao Hu Liu - Croton on Hudson NY, US
Chirag Suryakant Patel - Peekskill NY, US
Edmund Juris Sprogis - Underhill VT, US
Michelle Leigh Steen - Danbury CT, US
Brian Richard Sundlof - Beacon NY, US
Cornelia K. Tsang - Mohegan Lake NY, US
George Frederick Walker - New York NY, US

International Business Machines Corporation - Armonk NY

H01L 23/48
H01L 23/498
H01L 21/4763
H01L 29/40
H01L 23/52

257698, 257E23067, 257E23075, 257E23011, 257E25013, 257E21597, 257E23006, 257E23172, 257E23174, 257774, 257773, 257702, 257680, 257700, 257758

A carrier structure and method for fabricating a carrier structure with through-vias each having a conductive structure with an effective coefficient of thermal expansion which is less than or closely matched to that of the substrate, and having an effective elastic modulus value which is less than or closely matches that of the substrate. The conductive structure may include concentric via fill areas having differing materials disposed concentrically therein, a core of the substrate material surrounded by an annular ring of conductive material, a core of CTE-matched non-conductive material surrounded by an annular ring of conductive material, a conductive via having an inner void with low CTE, or a full fill of a conductive composite material such as a metal-ceramic paste which has been sintered or fused.

7880305, Feb 1, 2011

Nov 7, 2002

10/290049

Yu-Ting Cheng - Elmsford NY, US
Sherif A. Goma - Hawthorne NY, US
John Harold Magerlein - Yorktown Heights NY, US
Sampath Purushothaman - Yorktown Heights NY, US
Carlos Juan Sambucetti - Croton on Hudson NY, US
George Frederick Walker - New York NY, US

International Business Machines Corporation - Armonk NY

H01L 23/48
H01L 23/52
H01L 29/40

257761, 257762, 257E23145

The invention is the technology of providing a packaging intermediate product that can serve as an interface substrate that is to be positioned between different circuitry types where the dimensions are approaching the sub 100 micrometer range. The invention involves a dielectric wafer structure where the first and second area surfaces of the wafer are separated by a distance that is of the order of the electrical via design length, and an array of spaced vias through the wafer arranged with each via filled with metal surrounded by a chemical metal deposition promoting layer with each via terminating flush with a wafer surface. The wafer structure is achieved by forming an array of blind via openings through the first surface of the dielectric wafer to a depth approaching the via design length, lining the walls for adhesion enhancement, filling the blind via openings completely with a chemically deposited metal, removing material at the first wafer surface thereby planarizing the filled vias, and removing material at the second wafer surface thereby exposing the vias at the design length.

20060027934, Feb 9, 2006

Oct 3, 2005

11/242221

Daniel Edelstein - White Plains NY, US
Paul Andry - Yorktown Heights NY, US
Leena Buchwalter - Hopewell Junction NY, US
Jon Casey - Poughkeepsie NY, US
Sherif Goma - Hawthorne NY, US
Raymond Horton - Dover Plains NY, US
Gareth Hougham - Ossining NY, US
Michael Lane - Cortlandt Manor NY, US
Xiao Liu - Briarcliff Manor NY, US
Chirag Patel - Peekekill NY, US
Edmund Sprogis - Underhill VT, US
Michelle Steen - Danbury CT, US
Brian Sundlof - Verbank NY, US
Cornelia Tsang - Mohegan Lake NY, US
George Walker - New York NY, US
Yu-Ting Cheng - Hsinchu City, TW
Kenneth Ocheltree - Ossining NY, US
Robert Montoye - Austin TX, US

H01L 23/48

257774000

A carrier structure and method for fabricating a carrier structure with through-vias each having a conductive structure with an effective coefficient of thermal expansion which is less than or closely matched to that of the substrate, and having an effective elastic modulus value which is less than or closely matches that of the substrate. The conductive structure may include concentric via fill areas having differing materials disposed concentrically therein, a core of the substrate material surrounded by an annular ring of conductive material, a core of CTE-matched non-conductive material surrounded by an annular ring of conductive material, a conductive via having an inner void with low CTE, or a full fill of a conductive composite material such as a metal-ceramic paste which has been sintered or fused.

20090302454, Dec 10, 2009

Aug 11, 2009

12/462980

Yu- Ting Cheng - Elmsford NY, US
Sherif A. Goma - Hawthorne NY, US
John Harold Magerlein - Yorktown Heights NY, US
Sampath Purushothaman - Yorktown Heights NY, US
Carlos Juan Sambucetti - Croton on Hudson NY, US
George Frederick Walker - New York NY, US

H01L 23/48
H01L 21/768

257698, 438667, 438121, 257774, 257E23011, 257E21597, 257E21577

The invention is the technology of providing a packaging intermediate product that can serve as an interface substrate that is to be positioned between different circuitry types where the dimensions are approaching the sub 100 micrometer range. The invention involves a dielectric wafer structure where the first and second area surfaces of the wafer are separated by a distance that is of the order of the electrical via design length, and an array of spaced vias through the wafer arranged with each via filled with metal surrounded by a chemical metal deposition promoting layer with each via terminating flush with a wafer surface. The wafer structure is achieved by forming an array of blind via openings through the first surface of the dielectric wafer to a depth approaching the via design length, lining the walls for adhesion enhancement, filling the blind via openings completely with a chemically deposited metal, removing material at the first wafer surface thereby planarizing the filled vias, and removing material at the second wafer surface thereby exposing the vias at the design length.

20210264790, Aug 26, 2021

Feb 26, 2020

16/801844

- Armonk NY, US
Sherif A. Goma - Hawthorne NY, US
Chelsea Grindle - White Plains NY, US
Dakota Fried - New York NY, US
Kevin Chang - New York NY, US
Raphael Ezry - New York NY, US

G08G 1/16
G08G 1/01

A collision avoidance and road safety system is applied to a road network comprised of a plurality of road segments for a location to produce real time or dynamic forecasting of collision risk and root causes of the potential collision.