Shem O Ogadhoh

8399157, Mar 19, 2013

Dec 23, 2010

12/977813

Shem O. Ogadhoh - Beaverton OR, US

Intel Corporation - Santa Clara CA

G03F 1/36

430 5

Techniques are disclosed for using sub-resolution phased assist features (SPAF) in a lithography mask to improve through process pattern fidelity and/or mitigate inverted aerial image problems. The technique also may be used to improve image contrast in non-inverted weak image sites. The use of SPAF in accordance with some such embodiments requires no adjustment to existing design rules, although adjustments can be made to enable compliance with mask inspection constraints. The use of SPAF also does not require changing existing fab or manufacturing processes, especially if such processes already comprehend phased shift mask capabilities. The SPAFs can be used to enhance aerial image contrast, without the SPAFs themselves printing.

8404403, Mar 26, 2013

Jun 25, 2010

12/824037

Shem Ogadhoh - Beaverton OR, US
Raguraman Venkatesan - Portland OR, US
Kevin J. Hooker - Hillsboro OR, US
Sungwon Kim - Portland OR, US
Bin Hu - Portland OR, US
Vivek Singh - Portland OR, US
Bikram Baidya - Hillsboro OR, US
Prasad Narendra Atkar - Hillsboro OR, US
Seongtae Jeong - Portland OR, US

Intel Corporation - Santa Clara CA

G03F 1/68

430 5

Described herein is mask design and modeling for a set of masks to be successively imaged to print a composite pattern on a substrate, such as a semiconductor wafer. Further described herein is a method of double patterning a substrate with the set of masks. Also described herein is a method of correcting a drawn pattern of one of the mask levels based on a predicted pattern contour of the other of the mask levels. Also described herein is a method of modeling a resist profile contour for a mask level in which photoresist is applied onto a inhomogeneous substrate, as well as method of predicting a resist profile of a Boolean operation of two masks.

20060095887, May 4, 2006

Oct 29, 2004

10/977421

Robert Bigwood - Hillsboro OR, US
Shem Ogadhoh - Beaverton OR, US
Joseph Brandenburg - Portland OR, US

G06F 17/50

716019000, 716004000, 716021000

A correction for photolithography masks used in semiconductor and micro electromechanical systems is described. The correction is based on process windows. In one example, the invention includes evaluating a segment of an idealized photolithography mask at a plurality of different possible process variable values to estimate a corresponding plurality of different photoresist edge positions, comparing the estimated edge positions to a minimum critical dimension, and moving the segment on the idealized photolithography mask if the estimated edge positions do not satisfy the minimum critical dimension.

20130149638, Jun 13, 2013

Feb 7, 2013

13/762083

Shem OGADHOH - Beaverton OR, US
Raguraman VENKATESAN - Portland OR, US
Kevin J. HOOKER - Hillsboro OR, US
Sungwon KIM - Portland OR, US
Bin HU - Portland OR, US
Vivek SINGH - Portland OR, US
Bikram BAIDYA - Hillsboro OR, US
Prasad NARENDRA ATKAR - Hillsboro OR, US
Seongtae JEONG - Portland OR, US

G03F 1/36
G06F 17/50
G03F 1/68

430 5, 716 55

Described herein is mask design and modeling for a set of masks to be successively imaged to print a composite pattern on a substrate, such as a semiconductor wafer. Further described herein is a method of double patterning a substrate with the set of masks. Also described herein is a method of correcting a drawn pattern of one of the mask levels based on a predicted pattern contour of the other of the mask levels. Also described herein is a method of modeling a resist profile contour for a mask level in which photoresist is applied onto a inhomogeneous substrate, as well as method of predicting a resist profile of a Boolean operation of two masks.

20130216941, Aug 22, 2013

Mar 18, 2013

13/846319

Shem O. Ogadhoh - Beaverton OR, US
Charles H. Wallace - Portland OR, US
Ryan Pearman - San Jose CA, US
Sven Henrichs - San Jose CA, US
Arvind Sundaramurthy - Melno Park CA, US
Swaminathan Sivakumar - Beaverton OR, US

G03F 1/00

430 5

Techniques are disclosed for using sub-resolution phased assist features (SPAF) in a lithography mask to improve through process pattern fidelity and/or mitigate inverted aerial image problems. The technique also may be used to improve image contrast in non-inverted weak image sites. The use of SPAF in accordance with some such embodiments requires no adjustment to existing design rules, although adjustments can be made to enable compliance with mask inspection constraints. The use of SPAF also does not require changing existing fab or manufacturing processes, especially if such processes already comprehend phased shift mask capabilities. The SPAFs can be used to enhance aerial image contrast, without the SPAFs themselves printing. In addition, the SPAF phase etch depth can be optimized so as to make adjustments to a given predicted printed feature critical dimension.

20140053117, Feb 20, 2014

Dec 30, 2011

13/997565

Paul A. Nyhus - Portland OR, US
Shem O. Ogadhoh - Beaverton OR, US
Swaminathan Sivakumar - Beaverton OR, US
Seongtae Jeong - Portland OR, US

G06F 17/50

716 52

Techniques are provided for determining how thick or how deep to make the phased regions of a lithography mask. One example embodiment provides a method that includes: providing first mask layout design including a first test set, and providing a second mask layout design including a second test set, wherein the second test set is larger than the first test set; simulating critical dimensions through focus of structures of interest in the first test set for a range of phase depths/thicknesses, and selecting an initial preferred mask phase depth/thickness based on results of the simulating; and generating a fast thick-mask model (FTM) at the initial preferred phase depth/thickness, and correcting the second test set of the second mask layout design using the FTM, thereby providing an optimized mask layout design. A mask having the optimized mask layout design may be implemented to give the optimum patterning.

20220415897, Dec 29, 2022

Jun 25, 2021

17/358954

- Santa Clara CA, US
Travis W. LaJoie - Forest Grove OR, US
Elliot N. Tan - Portland OR, US
Kimberly Pierce - Beaverton OR, US
Shem Ogadhoh - West Linn OR, US
Abhishek A. Sharma - Portland OR, US
Bernhard Sell - Portland OR, US
Pei-Hua Wang - Hillsboro OR, US
Chieh-Jen Ku - Hillsboro OR, US

Intel Corporation - Santa Clara CA

H01L 27/108
H01L 29/786
H01L 29/66

A device structure includes a first interconnect line along a longitudinal direction and a second interconnect line parallel to the first interconnect line, where the first interconnect structure is within a first metallization level and the second interconnect line is within a second metallization level. A first transistor and a laterally separated second transistor are on a same plane above the second interconnect line, where a gate of the first transistor is coupled to the first interconnect line and a gate of the second transistor is coupled to the second interconnect line. A first capacitor is coupled to a first terminal of the first transistor and a second capacitor is coupled to a first terminal of the second transistor. A third interconnect line couples a second terminal of the first transistor with a second terminal of the second transistor.

20220320275, Oct 6, 2022

Jun 23, 2022

17/848224

- Santa Clara CA, US
Abhishek A. SHARMA - Portland OR, US
Chieh-Jen KU - Hillsboro OR, US
Shem OGADHOH - Beaverton OR, US
Allen B. GARDINER - Portland OR, US
Blake LIN - Portland OR, US
Yih WANG - Portland OR, US
Pei-Hua WANG - Beaverton OR, US
Jack T. KAVALIEROS - Portland OR, US
Bernhard SELL - Portland OR, US
Tahir GHANI - Portland OR, US

H01L 29/06
H01L 27/12
H01L 27/105
H01L 21/02
H01L 29/423
H01L 21/764
H01L 21/768

An integrated circuit includes a base, a first transistor structure on or above the base, and a second transistor structure on or above the base, where the second transistor structure is spaced from the first transistor structure. An insulator material at least partially encapsulates an airgap or other gas pocket laterally between the first transistor structure and the second transistor structure. The gas pocket is at least 5 nm in height and at least 5 nm wide according to an embodiment, and in some cases is as tall or taller than active device layers of the transistor structures it separates.