Inventors:
Sergei Bakarian - Sunnyvale CA
Julie Segal - Palo Alto CA
Assignee:
Heuristics Physics Laboratories, Inc. - San Jose CA
International Classification:
G06F 1750
US Classification:
716 5, 700110, 702 59, 703 14
Abstract:
A method for eliminating false failures saved by redundant paths during critical area analysis of an integrated circuit layout is described. Monte Carlo simulation generates simulated defects for an integrated circuit layout. Vertices significantly encroached by the simulated defects are identified. Information of predefined sets of vertices associated with individual nets including at least one of the identified vertices is retrieved. Failures resulting from the simulated defects are indicated only if all elements of at least one of the predefined sets of vertices are one of the identified vertices. The predefined sets of vertices are determined prior to circuit area analysis by extracting nets from an integrated circuit layout, and determining the predefined sets of vertices for individual nets such that the net fails only if all elements of individual of the predefined sets of vertices are significantly encroached by simulated defects.