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Sergei Bakarian Phones & Addresses

  • 2645 California St, Mountain View, CA 94040 (650) 917-9007
  • 2645 California St APT B, Mountain View, CA 94040 (650) 269-9965
  • 435 Acalanes Dr, Sunnyvale, CA 94086 (650) 938-3579
  • San Jose, CA
  • 2645 California St APT B, Mountain View, CA 94040 (650) 906-8547

Work

Position: Administrative Support Occupations, Including Clerical Occupations

Education

Degree: Associate degree or higher

Publications

Us Patents

Method For Eliminating False Failures Saved By Redundant Paths During Circuit Area Analysis On An Integrated Circuit Layout

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US Patent:
6810510, Oct 26, 2004
Filed:
Jun 11, 2002
Appl. No.:
10/167113
Inventors:
Sergei Bakarian - Sunnyvale CA
Julie Segal - Palo Alto CA
Assignee:
Heuristics Physics Laboratories, Inc. - San Jose CA
International Classification:
G06F 1750
US Classification:
716 5, 700110, 702 59, 703 14
Abstract:
A method for eliminating false failures saved by redundant paths during critical area analysis of an integrated circuit layout is described. Monte Carlo simulation generates simulated defects for an integrated circuit layout. Vertices significantly encroached by the simulated defects are identified. Information of predefined sets of vertices associated with individual nets including at least one of the identified vertices is retrieved. Failures resulting from the simulated defects are indicated only if all elements of at least one of the predefined sets of vertices are one of the identified vertices. The predefined sets of vertices are determined prior to circuit area analysis by extracting nets from an integrated circuit layout, and determining the predefined sets of vertices for individual nets such that the net fails only if all elements of individual of the predefined sets of vertices are significantly encroached by simulated defects.

Method For Avoiding False Failures Attributable To Dummy Interconnects During Defect Analysis Of An Integrated Circuit Design

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US Patent:
20030229867, Dec 11, 2003
Filed:
Jun 11, 2002
Appl. No.:
10/167039
Inventors:
Sergei Bakarian - Sunnyvale CA, US
Julie Segal - Palo Alto CA, US
International Classification:
G06F009/45
G06F017/50
US Classification:
716/005000
Abstract:
A method for avoiding false failures attributable to dummy interconnects during defect analysis of an integrated circuit design is described. Described processing includes retrieving conductivity layers information for an integrated circuit design from a GDSII formatted file; defining a dummy polygons layer and a target layer; restoring interconnect polygons from the conductivity layers information into the dummy polygons layer; copying the interconnect polygons from the dummy polygons layer to the target layer, except for dummy interconnect polygons; and performing defect analysis of the integrated circuit design using the target layer.

Extracting Comprehensive Design Guidance For In-Line Process Control Tools And Methods

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US Patent:
20150363537, Dec 17, 2015
Filed:
Jun 10, 2015
Appl. No.:
14/735596
Inventors:
- Milpitas CA, US
Sergei G. Bakarian - Mountain View CA, US
International Classification:
G06F 17/50
Abstract:
Methods and systems for extracting comprehensive design guidance for in-line process control of wafers are provided. One method includes automatically identifying potential marginalities in a design for a device to be formed on a wafer. The method also includes automatically generating information for the potential marginalities. The automatically generated information is used to set up process control for the wafer.
Sergei G Bakarian from Mountain View, CA, age ~60 Get Report