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Sean A Koontz

from Hollister, CA
Age ~54
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Also known as:
Sean Andrew Koontz, Sean Andre Koontz, Sean A Koentz
Phone and address:
630 Heatherwood Estates Dr, Hollister, CA 95023
(831) 630-3164
Related to:
Rebecca Hughes-HartogsLee Haris, 71Keilers LeeLinda Keilers, 83Karin Y
Connected to:
Andy Koontz, 46Becky S Koontz, 51Brenda C Koontz, 81Casey J Koontz, 39Chelsea Koontz, 34Fran Koontz, 78Hiram A Koontz, 96Jacob A Koontz, 37Jeanine M Koontz, 63Jennifer E Koontz, 43

Sean Koontz Phones & Addresses

  • 630 Heatherwood Estates Dr, Hollister, CA 95023 (831) 630-3164
  • Gilroy, CA
  • Salinas, CA
  • 405 Hidden Valley Rd, Watsonville, CA 95076
  • Royal Oaks, CA
  • Morgan Hill, CA
  • Santa Cruz, CA
  • San Luis Obispo, CA

Work

Company: Xilinx Mar 2000 Position: Senior manager - i and o applications

Education

School / High School: University of California, Santa Cruz 1995 to 1998

Industries

Semiconductors

Resumes

Resumes

Sean Koontz Photo 1

Senior Manager - I And O Applications

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Location:
San Francisco, CA
Industry:
Semiconductors
Work:
Xilinx
Senior Manager - I and O Applications
Amd-Vantis 1998 - 2000
Applications Engineer
Education:
University of California, Santa Cruz 1995 - 1998

Publications

Us Patents

Power Distribution System Built-In Self Test Using On-Chip Data Converter

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US Patent:
7138815, Nov 21, 2006
Filed:
Dec 24, 2003
Appl. No.:
10/746587
Inventors:
Mark A. Alexander - Boulder CO, US
Sean A. Koontz - Prunedale CA, US
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
G01R 31/02
US Classification:
324763
Abstract:
A packaged semiconductor device uses built-in self test to characterize voltage between points within the semiconductor die during a current discontinuity generated in the semiconductor die. The semiconductor die is operated to generate a current discontinuity, or several sequential current discontinuities, and the voltage is measured with an on-chip ADC. Measuring the voltage within the semiconductor die, rather than measuring at external test points, provides a more accurate prediction of device operation. Multiple test points are measured using a multiplexer, multiple ADCs, or by reconfiguring an FPGA. Impedance versus frequency information of the greater power distribution system connected to the semiconductor die is obtained by transforming the voltage and current through the semiconductor die measured during a current discontinuity.

Clock Auto-Phasing For Reduced Jitter

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US Patent:
8258845, Sep 4, 2012
Filed:
May 20, 2005
Appl. No.:
11/134117
Inventors:
Mark A. Alexander - San Francisco CA, US
Sean A. Koontz - Hollister CA, US
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
H03K 3/00
US Classification:
327291
Abstract:
The relative timing of triggering switching events in a circuit block of an IC device is dynamically adjusted in response to fluctuations in device's supply voltage to minimize clock jitter caused by supply voltage noise. A control circuit monitors supply voltage fluctuations, and in response thereto dynamically phase-shifts a clock signal that triggers the switching events so that the switching events occur during relatively quiet time intervals in which fluctuations in the supply voltage are minimal.
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Sean A Koontz from Hollister, CA, age ~54 Get Report