Satoru Takase

7183862, Feb 27, 2007

May 25, 2005

11/136817

Satoru Takase - Round Rock TX, US

Kabushiki Kaisha Toshiba - Tokyo

H03L 7/089

331 17, 331 25, 327157

Phased-lock loop (PLL) system and method for compensating current leakage where current leakage may include gate-leak current attributable to a gate capacitor. In particular, providing a compensation current to an input node of a voltage-controlled oscillator (VCO) to substantially compensate current leakage and therefore reduce PLL jitter. The PLL circuit includes a compensation charge pump which receives input from a counter and in turn provides a counter-value-proportional compensation current. The counter value increments and decrements according to up and down inputs from a phase frequency detector. The counter value is fixed when the PLL circuit is locked. The PLL circuit is driven to lock by the compensation charge pump, with or without the aid of another charge pump. While the PLL is locked, the compensation charge pump may provide a fixed counter-value-proportional compensation current.

7256630, Aug 14, 2007

May 25, 2005

11/137078

Satoru Takase - Round Rock TX, US

Kabushiki Kaisha Toshiba - Tokyo

H03L 7/06

327157, 327160

Systems and methods for reducing the effects of the operation of logic on a phase-locked loop (PLL) circuit are disclosed. These systems and methods may allow a PLL circuit to compensate for the anticipated effects of an instruction before, substantially simultaneously with, or after the execution of the instruction. More particularly, logic associated with the issue of instructions in a system may provide a signal to a PLL in the system based on an instruction. The PLL may then be adjusted to compensate for the anticipated effects of the instruction based on this control signal.

7366044, Apr 29, 2008

Jun 21, 2006

11/425438

Satoru Takase - Austin TX, US

Kabushiki Kaisha Toshiba - Tokyo

G11C 7/00
G11C 11/34
G11C 5/06
G11C 7/10

365205, 365 72, 36518901, 36518905, 365203

Systems and methods for reducing the latency of data transfers between memory cells by enabling data to be transferred directly between sense amplifiers in the memory system. In one embodiment, a memory system uses a conventional DRAM memory structure having a pair of first-level sense amplifiers, a second-level sense amplifier and control logic for the sense amplifiers. Each of the sense amplifiers is configured to be selectively coupled to a data line. In a direct data transfer mode, the control logic generates control signals that cause the sense amplifiers to transfer data from a first one of the first-level sense amplifiers (a source sense amplifier) to the second-level sense amplifier, and from there to a second one of the first-level sense amplifiers (a destination sense amplifier. ) The structure of these sense amplifiers is conventional, and the operation of the system is enabled by modified control logic.

7400213, Jul 15, 2008

May 25, 2005

11/137296

Satoru Takase - Round Rock TX, US

Kabushiki Kaisha Toshiba - Tokyo

H03H 7/38

333 33, 257692, 257698, 257737

Systems and methods for improved semiconductor device performance are disclosed. In particular, presented are improved semiconductor systems and methods for configuring conductors to reduce impedance variation caused by proximity and/or density and/or operation of connection-bumps. The invention includes adding impedance-reducing conductive features which add no additional functionality to the semiconductor device. The added features may be arranged in areas of sparse connection-bump density. Impedance-reducing conductive features may include metal lines added between functional metal lines, where placement between adjacent functional lines may vary. Impedance-reducing conductive features may be added to any one or combination of conductive layers, and added features may act upon any one or combination of functional features. Further, added features may be electrically active and responsive to semiconductor device operation. Also, methods for determining connection-bump density, which methods may be automated.

7492649, Feb 17, 2009

Nov 9, 2006

11/558045

Satoru Takase - Austin TX, US

Kabushiki Kaisha Toshiba - Tokyo

G11C 7/00

365195, 36518523, 36518522, 36518909

Systems and methods for reducing instability and writability problems arising from relative variations between a memory cell voltage (Vcell) and a logic voltage (Vdd) by inhibiting assertion of word line signals that enable accesses to the memory cells when the voltages are not within an acceptable operating range. One embodiment comprises a system having a critical condition detector configured to monitor the voltages and to determine whether the voltages are within an acceptable range. When the voltages are not within the acceptable range, the system inhibits assertion of the word lines to the memory cells. Memory accesses which fail because of the inhibited word line signals are retried by a memory controller when the critical conditions that caused the signals to be inhibited no longer exist.

7573735, Aug 11, 2009

Sep 8, 2006

11/530271

Satoru Takase - Austin TX, US
Takehito Sasaki - Austin TX, US

Kabushiki Kaisha Toshiba - Tokyo

G11C 11/00

365154, 36518906, 3651892, 365196, 36521012

Systems and methods for reducing instability and writability problems arising from relative variations between voltages at which memory cells and logic components that access the memory cells operate by inhibiting memory accesses when the voltages are not within an acceptable operating range. One embodiment comprises a pipelined processor having logic components which receive power at a first voltage and a set of SRAM cells which receive power at a second voltage. A critical condition detector is configured to monitor the first and second voltages and to determine whether the ratio of these voltages is within an acceptable range. When the voltages are not within the acceptable range, an exception is generated, and an exception handler stalls the processor pipeline to inhibit accesses to the SRAM cells. When the voltages return to the acceptable range, the exception handler resumes the pipeline and completes handling of the exception.

7808854, Oct 5, 2010

Feb 19, 2008

12/033198

Satoru Takase - Austin TX, US

Kabushiki Kaisha Toshiba - Tokyo

G11C 7/00

365205, 365189011, 365190

Systems and methods for reducing the latency of data transfers between memory cells by enabling data to be transferred directly between sense amplifiers in the memory system. In one embodiment, a memory system uses a conventional DRAM memory structure having a pair of first-level sense amplifiers, a second-level sense amplifier and control logic for the sense amplifiers. Each of the sense amplifiers is configured to be selectively coupled to a data line. In a direct data transfer mode, the control logic generates control signals that cause the sense amplifiers to transfer data from a first one of the first-level sense amplifiers (a source sense amplifier) to the second-level sense amplifier, and from there to a second one of the first-level sense amplifiers (a destination sense amplifier. ) The structure of these sense amplifiers is conventional, and the operation of the system is enabled by modified control logic.

7809890, Oct 5, 2010

Jul 6, 2005

11/175504

Satoru Takase - Round Rock TX, US
Yasuhiko Kurosawa - Kanagawa, JP

Kabushiki Kaisha Toshiba - Tokyo

G06F 13/00
G06F 13/28

711128, 711152, 711163, 711E12029

Systems and methods for increasing the yield of devices incorporating set-associative cache memories by selectively avoiding the use of cache entries that include defects. In one embodiment, a cache replacement manager determines in which of n possible entries data will be replaced. The cache replacement manager is configured to take into account whether each cache entry is defective when determining whether to select that entry as the destination entry for new data. The cache manager unit may implement a least-recently-used policy in selecting the cache entry in which the new data will be replaced. The cache replacement manager then treats any defective entries as if they hold the most recently used data, and thereby avoids selecting defective entries as the destination for new data. In one embodiment, the cache performs index translation before indexing into each set of cache entries in order to effectively redistribute defective entries among the indices.