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Satendra K Maurya

from Morrisville, NC
Age ~41
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Also known as:
Satendra Kumar Maurya, Saten Dra
Phone and address:
264 Begen St, Cary, NC 27560
Related to:
Surbhi Maurya
Connected to:
Ajay Maurya, 50Anuradha K Maurya, 44Atul S Maurya, 39Indu Maurya, 46Jaiprakash N Maurya, 61Neeraj Maurya, 42Vibha Maurya, 42Virendra Maurya, 40Vishnu Maurya, 43Caroline R Maus, 40

Satendra Maurya Phones & Addresses

  • 264 Begen St, Morrisville, NC 27560
  • Raleigh, NC
  • Tempe, AZ

Resumes

Resumes

Satendra Maurya Photo 1

Senior Design Engineer At Qualcomm

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Location:
950 south Terrace Rd, Tempe, AZ 85281
Industry:
Wireless
Work:
Qualcomm - Raleigh since Jan 2012
Senior Design Engineer
Nuon-inc Aug 2009 - Dec 2009
Design Engineer
Arizona State University Apr 2009 - May 2009
Teaching Assistant
Intel Corporation May 2008 - Dec 2008
Inter/co-op
Arizona State University Aug 2007 - May 2008
Teaching Assistant
Education:
Arizona State University 2009 - 2011
PhD, EE Arizona State University 2007 - 2009
MS, VLSI National Institute of Technology Tiruchirappalli 2000 - 2004
B Tech., Electronics and Communication Engineering
Skills:
Asic
Soc
Fpga
Rtl Design
Embedded Systems
Vlsi
Circuit Design
Computer Architecture
Verilog
Processors
Mixed Signal
Microprocessors
Vhdl
Low Power Design
Testing
Application Specific Integrated Circuits
Architecture
C
Field Programmable Gate Arrays
Electronics
Languages:
English
Hindi
Satendra Maurya Photo 2

Satendra Maurya

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Publications

Us Patents

Low Complexity Out-Of-Order Issue Logic Using Static Circuits

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US Patent:
20120278593, Nov 1, 2012
Filed:
Apr 30, 2012
Appl. No.:
13/459964
Inventors:
Lawrence T. Clark - Phoenix AZ, US
Siddhesh Mhambrey - Austin TX, US
Satendra Kumar Maurya - Tempe AZ, US
Assignee:
Arizona Technology Enterprises, LLC - Scottsdale AZ
International Classification:
G06F 9/30
US Classification:
712215, 712E09016
Abstract:
Instruction issue circuits are disclosed that are configured to issue multiple instructions within a superscalar pipeline of a microprocessor. The instruction issue circuit includes an instruction queue that stores instructions. A ready generation circuit is operably associated with the instruction queue and generates ready signals that indicate which instructions in the instruction queue are ready for execution. To simplify the instruction issue circuit, the instruction issue circuit has group blocks. Each group block receives a different group of the ready signals corresponding to a different group of the instructions. Each group block generates a group output indicating a group set within the corresponding group of the instructions that has a highest instruction execution priority and are ready for execution. By splitting the ready signals into groups, the groups of ready signals can be processed in parallel thereby reducing both the resulting delay and complexity of the instruction issue circuit.

Longest Prefix Match Internet Protocol Content Addressable Memories And Related Methods

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US Patent:
20120063189, Mar 15, 2012
Filed:
May 26, 2010
Appl. No.:
13/321309
Inventors:
Satendra Kumar Maurya - Tempe AZ, US
Lawrence T. Clark - Phoenix AZ, US
Assignee:
Arizona Board of Regents for and on Behalf of Arizona State University - Scottsdale AZ
International Classification:
G11C 15/00
US Classification:
365 4917, 365 4918
Abstract:
Embodiments of content addressable memories for internet protocol devices and operations are described herein. Other examples and related methods are also disclosed herein.

Pipelining An Asynchronous Memory Reusing A Sense Amp And An Output Latch

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US Patent:
20160293234, Oct 6, 2016
Filed:
Jun 18, 2015
Appl. No.:
14/742706
Inventors:
- San Diego CA, US
Satendra Kumar MAURYA - Raleigh NC, US
Kunal GARG - Raleigh NC, US
Chiaming CHAI - Cary NC, US
Chintan SHAH - Apex NC, US
International Classification:
G11C 7/22
G11C 7/10
G11C 7/06
Abstract:
An asynchronous memory includes a memory array, a sense amplifier, an output latch, and a controller. In response to a clock signal from an external circuit requesting a read operation, the controller provides the clock signal to the memory array to read data, and controls the sense amplifier and the output latch to provide the functionality of a flip-flop master and slave so that the read operation delay through the output latch to the external circuit is removed from a first read cycle of two sequential read cycles.

Circuits For Voltage Or Current Biasing Static Random Access Memory (Sram) Bitcells During Sram Reset Operations, And Related Systems And Methods

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US Patent:
20150036418, Feb 5, 2015
Filed:
Oct 28, 2013
Appl. No.:
14/064297
Inventors:
- San Diego CA, US
Satendra Kumar Maurya - Raleigh NC, US
Assignee:
QUALCOMM Incorporated - San Diego CA
International Classification:
G11C 11/412
US Classification:
365154
Abstract:
Circuits for voltage or current biasing static random access memory (SRAM) bitcells during SRAM reset operations are disclosed. Related systems and methods are also disclosed. To reset a plurality of SRAM bitcells in a single reset operation, a biasing circuit is provided and coupled to the plurality of SRAM bitcells. The biasing circuit is configured to apply a voltage or current bias to the SRAM bitcells during a reset operation after power provided to the SRAM bitcells is collapsed to a collapsed power level below an operational power level. The bias is applied as the power to the SRAM bitcells is restored to an operational power level, thus forcing the SRAM bitcells into a desired state. In this manner, the SRAM bitcells can be reset in a single reset operation without need for an increased drive strength from a reset circuit and without need to provide specialized SRAM bitcells.
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Satendra K Maurya from Morrisville, NC, age ~41 Get Report