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Samar Pradeep Naik

from Phoenix, AZ
Age ~44
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Also known as:
Samar P Naik
Related to:
Garrett M Ritz, 44Praful C Desai, 76Aruna P Naik, 73Pradeep Y Naik, 80Paras P Naik, 46Bharti J Desai, 62Janak D Desai, 63
Connected to:
Abhijeet A Naik, 55Abhijit S Naik, 42Amee P Naik, 47Ameya A Naik, 34Anilkumar R Naik, 56Apoorv Naik, 38Bindi Naik, 45Chaitali D Naik, 27Chinmay Naik, 37Deepali Naik, 43

Samar Naik Phones & Addresses

  • Phoenix, AZ
  • 732 Lenore St, Addison, IL 60101 (630) 543-4463
  • 2400 Arizona Ave, Chandler, AZ 85225
  • Champaign, IL
  • Maricopa, AZ
  • 1489 W Enfield Way, Chandler, AZ 85286

Work

Company: Microchip technology Aug 2012 Address: Chandler, AZ Position: Technical staff design engineer

Education

Degree: BS School / High School: University of Illinois at Urbana-Champaign 1998 to 2002 Specialities: Computer Engineering

Skills

Systemverilog • Integrated Circuit Design • Rtl Design • Asic • Static Timing Analysis • Soc • Semiconductors • Verilog • Microcontrollers • Modelsim • Primetime • Mixed Signal • Simulations • Low Power Design • Cmos • Digital Design • Ic • Dft • Rtl Coding • Logic Synthesis • Fpga • Functional Verification • Logic Design • Timing Closure • Vlsi • Atpg • Low Power Design • Simulation

Industries

Semiconductors

Resumes

Resumes

Samar Naik Photo 1

Team Lead, Digital Design

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Location:
330 east Pierce St, Phoenix, AZ 85004
Industry:
Semiconductors
Work:
Microchip Technology - Chandler, AZ since Aug 2012
Technical Staff Design Engineer
Microchip Technology - Chandler, AZ Feb 2006 - Aug 2012
Technical Staff Design Engineer
Microchip Technology - Chandler, AZ May 2010 - Jul 2012
Design Manager
Freescale Semiconductor May 2004 - Jan 2006
Digital Design Engineer
Motorola Feb 2003 - May 2004
Rotational Engineer
Education:
University of Illinois at Urbana-Champaign 1998 - 2002
BS, Computer Engineering
Skills:
Systemverilog
Integrated Circuit Design
Rtl Design
Asic
Static Timing Analysis
Soc
Semiconductors
Verilog
Microcontrollers
Modelsim
Primetime
Mixed Signal
Simulations
Low Power Design
Cmos
Digital Design
Ic
Dft
Rtl Coding
Logic Synthesis
Fpga
Functional Verification
Logic Design
Timing Closure
Vlsi
Atpg
Low Power Design
Simulation

Publications

Us Patents

Dynamic Pause Period Calculation For Serial Data Transmission

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US Patent:
20140258566, Sep 11, 2014
Filed:
Mar 6, 2014
Appl. No.:
14/199785
Inventors:
- Chandler AZ, US
Samar Naik - Chandler AZ, US
International Classification:
G06F 11/30
US Classification:
710 18
Abstract:
A serial transmission peripheral device for transmitting serial transmission data with a variable data length includes a pulse forming unit; and a register programmable to set a desired transmission length. The peripheral device is operable to determine an actual transmission length and calculate a length of a pause pulse and to add the pause pulse at the end of a transmission to generate a transmission having a constant length.
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Samar Pradeep Naik from Phoenix, AZ, age ~44 Get Report