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Sai P Dhanraj

from Monte Sereno, CA
Age ~40
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Also known as:
Sai Prashanth Dhanraj
Related to:
Srinivas Dhanraj, 49Dhanraj A
Connected to:
Bibi D Dhanraj, 42Doodmatee E Dhanraj, 70Hemant K Dhanrajani, 48Jamey Dhanraj, 51Melissa R Dhanraj, 30Peter Dhanraj, 76Stephen S Dhanraj, 64Vijay Dhanraj, 41Vijay S Dhanrajani, 48Robert L Dhans, 59

Sai Dhanraj Phones & Addresses

  • Monte Sereno, CA
  • Sunnyvale, CA
  • San Jose, CA
  • Santa Clara, CA
  • Milpitas, CA

Work

Company: Cypress semiconductor corporation Feb 2018 Position: Senior staff marketing

Education

Degree: Masters School / High School: San Jose State University 2007 to 2008 Specialities: Electrical Engineering

Skills

Cmos • Semiconductors • Ic • Mixed Signal • Vlsi • Soc • Analog Circuit Design • Semiconductor Industry • Failure Analysis • Eda • Verilog • Circuit Design • Silicon • Jmp

Industries

Semiconductors

Resumes

Resumes

Sai Dhanraj Photo 1

Senior Staff Marketing

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Location:
3901 north 1St St, San Jose, CA 95113
Industry:
Semiconductors
Work:
Cypress Semiconductor Corporation
Senior Staff Marketing
Cypress Semiconductor Corporation
Principal Techology Development Engineer
Cypress Semiconductor Corporation Jul 2012 - Jun 2014
Technology Development Engineer Staff
Cypress Semiconductor Corporation Jul 2012 - Jun 2014
Senior Staff Technology Development Engineer at Cypress Semiconductor Corporation
Cypress Semiconductor Corporation Nov 2008 - Jul 2012
Senior Technology Development Engineer
Education:
San Jose State University 2007 - 2008
Masters, Electrical Engineering Portland State University 2006 - 2006
Master of Science, Masters, Electrical Engineering P.g. College of Law, Basheerbagh 2002 - 2006
Bachelor of Engineering, Bachelors, Engineering, Communications
Skills:
Cmos
Semiconductors
Ic
Mixed Signal
Vlsi
Soc
Analog Circuit Design
Semiconductor Industry
Failure Analysis
Eda
Verilog
Circuit Design
Silicon
Jmp

Publications

Us Patents

Circuit With Electrostatic Discharge Protection

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US Patent:
8283727, Oct 9, 2012
Filed:
Dec 11, 2009
Appl. No.:
12/636596
Inventors:
Andrew Walker - Mountain View CA, US
Helmut Puchner - Santa Clara CA, US
Sai Dhanraj - Milpitas CA, US
Kevin Jang - Santa Clara CA, US
Assignee:
Cypress Semiconductor Corporation - San Jose CA
International Classification:
H01L 23/62
US Classification:
257355, 257E29012
Abstract:
A circuit with electrostatic discharge protection is described. In one case, the circuit includes trigger device configured to protect a component connected to a node of the circuit during an electrostatic discharge event, the trigger device includes an isolation structure interposed between a gate oxide layer and an extended drain region. A portion of the extended drain region proximate the isolation structure is substantially metal-free.

Esd Clamp With A Layout-Alterable Trigger Voltage And A Holding Voltage Above The Supply Voltage

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US Patent:
20150200168, Jul 16, 2015
Filed:
Dec 4, 2014
Appl. No.:
14/560135
Inventors:
- San Jose CA, US
Roger Bettman - Los Altos CA, US
Sai Prashanth Dhanraj - San Jose CA, US
Dung Ho - Sunnyvale CA, US
Iman Rezanezhad Gatabi - Sunnyvale CA, US
Andrew Walker - Mountain View CA, US
International Classification:
H01L 23/60
H01L 27/02
H01L 27/06
Abstract:
An ESD device that includes a gate and an n-drain region isolated from the gate and formed at least partially within an n-well region, which in turn is formed at least partially within a deep n-well region. The doping levels of the n-drain region, the n-well region and the deep n-well region are in a descending order. The ESD device has trigger and holding voltages, above the operation voltage of its protected circuit, which are layout-configurable by altering the distance between the n-drain and a side edge of the n-well region.
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Sai P Dhanraj from Monte Sereno, CA, age ~40 Get Report