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Romesh M Jessani

from Austin, TX
Age ~60
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Also known as:
Romesh B Jessani, Romess Jessani, H Jessani
Phone and address:
3419 Kissman Dr, Austin, TX 78728
(512) 246-8138
Related to:
Allison M Jessani, 26Robin JessaniVinod M JessaniNarendra Chawla, 79Madhu Chawla
Connected to:
Sari V Jessann, 35Jacob B Jessar, 37Jamie A Jessar, 65Ralph A Jessar, 102Sharon R Jessar, 70Brenda M Jesse, 58Grace E Jesse, 76Hollie L Jesse, 48Jacob M Jesse, 30Jamie J Jesse, 43

Romesh Jessani Phones & Addresses

  • 3419 Kissman Dr, Austin, TX 78728 (512) 246-8138
  • 8420 Bangor Bnd, Austin, TX 78758
  • 10912 Debra Ave, Granada Hills, CA 91344 (818) 787-9640
  • Van Nuys, CA
  • Richardson, TX

Work

Company: Sigmatel 2003 to 2006 Position: Member of technical staff

Education

Degree: M.S. School / High School: The University of Texas at Dallas 1989 to 1991 Specialities: E.E.

Emails

r***[email protected]

Industries

Semiconductors

Resumes

Resumes

Romesh Jessani Photo 1

Romesh Jessani

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Location:
Austin, TX
Industry:
Semiconductors
Work:
SIGMATEL 2003 - 2006
Member Of Technical Staff
EQUATOR TECHNOLOGIES 1998 - 2002
Member Of Technical Staff
ROSS TECHNOLOGIES 1996 - 1998
Verification Engineer
MOTOROLA 1991 - 1996
Logic Design Engineer
ADVANCED MICRO DEVICES 1991 - 1991
Contract Circuit Design
Education:
The University of Texas at Dallas 1989 - 1991
M.S., E.E. Kurukshetra University 1983 - 1988
B.S., Electronics & Communications

Publications

Us Patents

Patching Rom Code

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US Patent:
7739469, Jun 15, 2010
Filed:
Nov 8, 2005
Appl. No.:
11/268827
Inventors:
Romesh Mangho Jessani - Austin TX, US
Antonio Torrini - Austin TX, US
Robert Koelling - Austin TX, US
David Baker - Austin TX, US
Assignee:
Freescale Semiconductor, Inc. - Austin TX
International Classification:
G06F 12/00
G06F 12/02
G06F 12/12
US Classification:
711165, 711103, 711170, 717168
Abstract:
An instruction set is executed from Read Only Memory (ROM). When a current instruction in the instruction set corresponds to a reserved patch memory block of ROM, a Random Access Memory (RAM) index and a ROM return address are loaded into a memory map, and a program counter is set to a first reserved ROM address. After jumping the program counter to the first reserved ROM address, the program counter is jumped to RAM based on the RAM index to execute a patch code, which includes at least one instruction to set the program counter to a second reserved ROM address. When the program counter equals the second reserved ROM address, the ROM return address is retrieved. Then the instruction set is executed from ROM based on the ROM return address.

System On A Chip Integrated Circuit, Processing System And Methods For Use Therewith

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US Patent:
20070083713, Apr 12, 2007
Filed:
Oct 11, 2005
Appl. No.:
11/247740
Inventors:
Antonio Torrini - Austin TX, US
Robert Koelling - Austin TX, US
Romesh Mangho Jessani - Austin TX, US
David Baker - Austin TX, US
International Classification:
G06F 12/00
US Classification:
711125000
Abstract:
A method of executing a program using a processor is implemented by executing a first main program segment stored in a ROM device until a first ROM instruction address, corresponding to one of a first sequence of ROM instructions, matches one of a plurality of a patch addresses stored in a patch register set. In response to this matching, a first patch program segment, stored in a RAM device, is executed.

Processor And Method For Out-Of-Order Execution Of Instructions Based Upon An Instruction Parameter

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US Patent:
58729488, Feb 16, 1999
Filed:
Mar 15, 1996
Appl. No.:
8/616613
Inventors:
Soummya Mallick - Austin TX
Rajesh Bikhubhai Patel - Austin TX
Romesh Mangho Jessani - Austin TX
Michael Putrino - Austin TX
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 928
US Classification:
395390
Abstract:
A processor and method for out-of-order execution of instructions are disclosed which fetch a first and a second instruction, wherein the first instruction precedes the second instruction in a program order. A determination is made whether execution of the second instruction is subject to execution of the first instruction. In response to a determination that execution of the second instruction is subject to execution of the first instruction, the second instruction is selectively executed prior to the first instruction in response to a parameter of at least one of the first and second instructions. In one embodiment, the parameter is an execution latency parameter of the first and second instructions.

Method And Apparatus For Dynamic Allocation Of Registers For Intermediate Floating-Point Results

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US Patent:
58059164, Sep 8, 1998
Filed:
Nov 27, 1996
Appl. No.:
8/758017
Inventors:
Soummya Mallick - Austin TX
Michael Putrino - Austin TX
Romesh Mangho Jessani - Austin TX
Assignee:
International Business Machines Corporation - Armonk NY
Motorola, Inc. - Schaumburg IL
International Classification:
G06F 938
US Classification:
39580023
Abstract:
The present invention relates to a multiple stage execution unit for executing instructions in a microprocessor having a plurality of rename registers for storing execution results, an instruction cache for storing instructions, each instruction being associated with a rename register, a sequencer unit for providing an instruction to the execution unit, and a data cache for providing data to the execution unit. In one version, the execution unit includes a first stage which generates an intermediate result from the data according to an instruction; a means for providing a first portion of the intermediate result to an intermediate register; a means for providing a second portion of the intermediate result to a rename register associated with the instruction; a means for passing the first portion from the intermediate register to a second stage of the execution unit; a means for passing the second portion from the rename register to the second stage of the execution unit; wherein the second stage of the execution unit operates on the first and second portions according to the instruction.

Processor And Method For Executing A Branch Instruction And An Associated Target Instruction Utilizing A Single Instruction Fetch

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US Patent:
57649405, Jun 9, 1998
Filed:
Nov 27, 1996
Appl. No.:
8/757186
Inventors:
Soummya Mallick - Austin TX
Rajesh Bhikhubhai Patel - Austin TX
Romesh Mangho Jessani - Austin TX
Assignee:
International Business Machines Corporation - Armonk NY
Motorola, Inc. - Schaumburg IL
International Classification:
G06F 938
US Classification:
395382
Abstract:
A processor and method of executing instructions within a processor are disclosed, which permit both a branch instruction and a target instruction of the branch instruction to be executed in response to a single instruction fetch. In accordance with an illustrative embodiment, the processor, which has an associated memory, simultaneously fetches a plurality of instructions from the memory. Branch instructions among the plurality of instructions are then detected. In response to a detection of a branch instruction among the plurality of instructions, a determination is made whether a target instruction to be executed in response to execution of the branch instruction is one of the plurality of instructions. In response to a determination that the target instruction is one of the plurality of instructions, the processor executes the target instruction without making an additional instruction fetch.

Method And System Of Implementing An Early Data Dependency Resolution Mechanism In A High-Performance Data Processing System Utilizing Out-Of-Order Instruction Issue

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US Patent:
58128123, Sep 22, 1998
Filed:
Nov 4, 1996
Appl. No.:
8/740911
Inventors:
Muhammad Nural Afsar - Solana Beach CA
Romesh Mangho Jessani - Austin TX
Soummya Mallick - Austin TX
Robert Greg McDonald - Austin TX
Mukesh Sharma - Austin TX
Assignee:
International Business Machines Corporation - Armonk NY
Motorola, Inc. - Schaumburg IL
International Classification:
G06F 938
US Classification:
395392
Abstract:
A method and system of implementing an early data dependency resolution mechanism for a high-performance data processing system that utilizes out-of-order instruction issue is disclosed. In accordance with the present disclosure, an instruction cache and a register-dependency cache are provided. The instruction cache has multiple cache lines, and each of these cache lines is capable of storing multiple instructions. The register-dependency cache contains an identical number of cache lines as in the instruction cache, and each of the cache lines within the register-dependency cache is capable of storing an identical number of register-dependency units as instructions in each of the cache lines within the instruction cache. In a single processor cycle, a group of register-dependency units are fetched from the register-dependency cache. All register-dependency units that have no forward data dependency within the group of register-dependency units are identified utilizing an Instruction Dispatch Unit.

Method And System For Processing A Multiple-Register Instruction That Permit Multiple Data Words To Be Written In A Single Processor Cycle

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US Patent:
59130547, Jun 15, 1999
Filed:
Dec 16, 1996
Appl. No.:
8/768059
Inventors:
Soummya Mallick - Austin TX
Rajesh Bhikubhai Patel - Austin TX
Albert John Loper - Cedar Park TX
Romesh Mangho Jessani - Austin TX
Assignee:
International Business Machines Corporation - Armonk NY
Motorola, Inc. - Schaumburg IL
International Classification:
G06F 900
G06F 930
US Classification:
395561
Abstract:
A processor and method of processing a multiple-register instruction are described. The processor includes execution circuitry and a set of registers, which are each capable of storing a data word. A multiple-register instruction specifying a plurality of data words that are to be written to a corresponding plurality of registers within the set of registers is dispatched to the execution circuitry. In response to receipt of the multiple-register instruction, the execution circuitry executes the multiple-register instruction, such that at least two data words among the plurality of data words are written to at least two corresponding registers among the plurality of registers during a single cycle of the processor.

Cache Memory Management System Having Reduced Reloads To A Second Level Cache For Enhanced Memory Performance In A Data Processing System

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US Patent:
57377510, Apr 7, 1998
Filed:
Mar 26, 1996
Appl. No.:
8/622254
Inventors:
Rajesh Bhikhubhai Patel - Austin TX
Sung-Ho Park - Austin TX
Romesh Mangho Jessani - Austin TX
Belliappa Manavattira Kuttanna - Austin TX
Assignee:
Intellectual Business Machines Corporation - Armonk NY
Motorola, Inc. - Schaumburg IL
International Classification:
G06F 1212
US Classification:
711133
Abstract:
A data processing system having enhanced memory performance is provided. The data processing system comprises a processor that issues memory requests, a multilevel storage system including a first level cache, a second level cache, and a main memory connected to the processor in a memory hierarchy, and a memory controller. The memory controller retrieves a cache line from main memory, when a memory request for the cache line is received from the processor at the first level cache that causes a miss in both the first level cache and the second level cache. The memory controller loads the retrieved cache line in both the first level cache and the second level cache if the received memory request is a load request, and loads the retrieved cache line in only the first level cache and not the second level cache if the received memory request is a store request. The resultant reduction in reloads to the second level cache enhances memory performance by allowing immediate execution of subsequent memory requests to the second level cache and producing a higher hit rate as a result of the reduction in castouts from the second level cache.
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Romesh M Jessani from Austin, TX, age ~60 Get Report