Resumes
Resumes
Roger Verhelst Phones & Addresses
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15 Bay Cir, Colchester, VT 05446 (802) 864-6333
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203 Bay Rd, Colchester, VT 05446 (802) 864-6333
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203 Bay Cir, Colchester, VT 05446 (802) 864-6333
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183 Robin Ln, Milton, VT 05468
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626 35Th St SE, Cedar Rapids, IA 52403 (319) 366-4291 (515) 366-4291
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Shelburne, VT
Publications
Us Patents
Device Contact Structure And Method For Fabricating Same
View pageUS Patent:
60906731, Jul 18, 2000
Filed:
Oct 20, 1998
Appl. No.:
9/175304
Inventors:
Archibald J. Allen - Shelburne VT
Toshiharu Furukawa - Essex Junction VT
Edward F. O'Neil - Essex Junction VT
Mark C. Hakey - Milton VT
Roger A. Verhelst - Colchester VT
David V. Horak - Essex Junction VT
Toshiharu Furukawa - Essex Junction VT
Edward F. O'Neil - Essex Junction VT
Mark C. Hakey - Milton VT
Roger A. Verhelst - Colchester VT
David V. Horak - Essex Junction VT
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 21336
H01L 213205
H01L 213205
US Classification:
438301
Abstract:
The present invention overcomes the difficulties found in the background art by providing a direct low resistive contact between devices on a semiconductor chip without excessive current leakage. Current leakage is prevented in the preferred design by using silicon on insulator (SOI) construction for the chip. By constructing the direct contact over an insulator, such as silicon dioxide, current leakage is minimized. The preferred embodiment uses silicide to connect a polysilicon gate to a doped region of the substrate. An alternative embodiment of the present invention provides for the use of conductive studs to electrically connect devices. An increased density of approximately twenty percent may be realized using the present invention.
Special Mode Enable Transparent To Normal Mode Operation
View pageUS Patent:
56595085, Aug 19, 1997
Filed:
Dec 6, 1995
Appl. No.:
8/568411
Inventors:
Steven Harley Lamphier - St. Albans VT
Kevin George Petrunich - Essex Junction VT
Harold Pilo - Underhill VT
Ronald DeSales Rossi - Swanton VT
Roger Andrew Verhelst - Colchester VT
Paul Stafford Zerr - Gilbert AZ
Kevin George Petrunich - Essex Junction VT
Harold Pilo - Underhill VT
Ronald DeSales Rossi - Swanton VT
Roger Andrew Verhelst - Colchester VT
Paul Stafford Zerr - Gilbert AZ
Assignee:
International Business Machine Corporation
International Classification:
G11C 700
G11C 800
G11C 800
US Classification:
365201
Abstract:
Circuit and method are presented for activating/deactivating a special operational mode at power-on of an integrated circuit device having no industry defined test state and/or dedicated test pin. The operational mode is enabled upon powering on the integrated circuit combined with detection of a predefined pattern of a first logic state and a second logic state clocked in successive cycles within a first standard input signal, such as an output enable signal, for a normal operating mode of the device. Special non-functional processing is then performed, such as reading prestored identification data from the integrated circuit and/or testing the integrated circuit via embedded test circuitry including boundary scan or other diagnostic circuitry. This special operational mode is deactivated upon receipt at the integrated circuit device of a second standard input signal, such as a write signal for a random access memory (RAM) device, of a predefined logic state (e. g. , write enable state).