Inventors:
Navaz M. Lulla - Fremont CA, US
Ramin Ighani - Santa Clara CA, US
Roger J. Bettman - Los Altos CA, US
Assignee:
Cypress Semiconductor Corporation - San Jose CA
International Classification:
G01R 31/28
Abstract:
An integrated circuit including a first cell configured to perform boundary scan testing, and an I/O node coupled to the first cell, wherein the I/O node is configured to carry a first differential signal. A level translator may be coupled between the I/O node and the first cell, wherein the level translator is configured to translate the first differential signal into a single ended signal. A level translator may be coupled between the I/O node and the first cell, wherein the level translator is configured to translate a single ended signal into the first differential signal. Core logic may be coupled to the first cell, wherein the core logic is configured to process a second differential signal, and a level translator may be coupled between the core logic and the first cell, wherein the level translator is configured to translate the second differential signal into a single ended signal.