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Roger Bettman Phones & Addresses

  • Mountain View, CA
  • 1862 Colleen Dr, Los Altos Hills, CA 94024 (650) 969-6488 (650) 224-6798
  • Los Altos, CA
  • San Jose, CA
  • Phoenix, AZ
  • 1862 Colleen Dr, Los Altos, CA 94024

Education

Degree: Associate degree or higher

Emails

r***n@excite.com

Publications

Us Patents

Cpld High Speed Path

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US Patent:
6486701, Nov 26, 2002
Filed:
Jun 12, 2000
Appl. No.:
09/617601
Inventors:
Roger Bettman - Los Altos CA
Assignee:
Cypress Semiconductor Corp. - San Jose CA
International Classification:
H03K 19173
US Classification:
326 38, 326 47
Abstract:
An apparatus comprises two or more memory elements connected in parallel and programmed alike, where the memory elements comprise a high speed path of a programmable logic device.

Design Architecture For A Parallel And Serial Programming Interface

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US Patent:
6510487, Jan 21, 2003
Filed:
Jan 24, 1996
Appl. No.:
08/592868
Inventors:
S. Babar Raza - Sunnyvale CA
Anita X. Meng - Milpitas CA
Donald A. Krall - Cuportino CA
Khaldoon S. Abugharbieh - Sunnyvale CA
Roger J. Bettman - Los Altos CA
Assignee:
Cypress Semiconductor Corp. - San Jose CA
International Classification:
G06F 1300
US Classification:
711100, 711211, 36518902, 365220, 365221, 710 51, 710 62, 710305
Abstract:
The present invention provides an integrated parallel and serial programming interface that can be selected between either a parallel programming mode or a serial programming mode. The present invention provides a control logic circuit for selecting between the parallel and serial modes. The present invention also includes a parallel and serial detection circuit. The control logic sends a signal to an interface circuit that selects between a serial programming mode and a parallel programming mode based on the outputs of the parallel and serial detection circuits.

Reduced Product Term Carry Chain

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US Patent:
6708190, Mar 16, 2004
Filed:
Jun 5, 2000
Appl. No.:
09/587708
Inventors:
Christopher W. Jones - Pleasanton CA
Roger Bettman - Los Altos CA
Assignee:
Cypress Semiconductor Corp. - San Jose CA
International Classification:
G06F 738
US Classification:
708230, 326 39
Abstract:
A programmable logic device comprising one or more macrocells and a product term array. The macrocells may comprise logic that may be configured to (i) generate and propagate a carry signal and (ii) generate a sum bit. The product term array may comprise two product terms per macrocell.

Input Gate Protection Circuit And Method

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US Patent:
6768618, Jul 27, 2004
Filed:
Aug 1, 2002
Appl. No.:
10/210279
Inventors:
Sanjeev Kumar Maheshwari - Santa Clara CA
Roger Jay Bettman - Los Altos CA
Assignee:
Cypress SemiConductor, Corp. - San Jose CA
International Classification:
H02H 322
US Classification:
361 56, 361111
Abstract:
An input gate protection circuit has a pass transistor having a source coupled to an input signal. A first voltage range control circuit is coupled to a gate of the pass transistor. A second voltage range is control circuit coupled to the gate of the pass transistor.

Boundary Scan Register For Differential Chip Core

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US Patent:
6990618, Jan 24, 2006
Filed:
Dec 3, 2002
Appl. No.:
10/309664
Inventors:
Navaz M. Lulla - Fremont CA, US
Ramin Ighani - Santa Clara CA, US
Roger J. Bettman - Los Altos CA, US
Assignee:
Cypress Semiconductor Corporation - San Jose CA
International Classification:
G01R 31/28
US Classification:
714727
Abstract:
An integrated circuit including a first cell configured to perform boundary scan testing, and an I/O node coupled to the first cell, wherein the I/O node is configured to carry a first differential signal. A level translator may be coupled between the I/O node and the first cell, wherein the level translator is configured to translate the first differential signal into a single ended signal. A level translator may be coupled between the I/O node and the first cell, wherein the level translator is configured to translate a single ended signal into the first differential signal. Core logic may be coupled to the first cell, wherein the core logic is configured to process a second differential signal, and a level translator may be coupled between the core logic and the first cell, wherein the level translator is configured to translate the second differential signal into a single ended signal.

Trench-Based Capacitor For Integrated Circuits

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US Patent:
7166902, Jan 23, 2007
Filed:
Nov 15, 2004
Appl. No.:
10/988812
Inventors:
Fuad Badrieh - Santa Clara CA, US
Feng Dai - San Jose CA, US
Bartosz Banachowicz - Santa Clara CA, US
Roger J. Bettman - Los Altos CA, US
Assignee:
Cypress Semiconductor Corporation - San Jose CA
International Classification:
H01L 21/425
US Classification:
257532, 257303, 257534, 257535
Abstract:
In one embodiment, an electrically conductive trench in an integrated circuit allows for the formation of capacitors between the trench and other portions of the integrated circuit. For example, a capacitor may be formed between the trench and an electrically conductive line. Among other advantages, the capacitor provides a relatively large capacitance while occupying a relatively small area.

Content Addressable Memory (Cam) Cell Bit Line Architecture

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US Patent:
7173837, Feb 6, 2007
Filed:
Aug 31, 2004
Appl. No.:
10/931960
Inventors:
Roger Bettman - Los Altos CA, US
Eric H. Voelkel - Ben Lomond CA, US
Assignee:
Netlogic Microsystems, Inc. - Mountain View CA
International Classification:
G11C 15/00
G11C 11/00
G11C 8/00
G06F 13/00
US Classification:
365 49, 365154, 36523005, 711108, 711117, 711118, 711128
Abstract:
A ternary content addressable memory (TCAM) cell () can include two memory elements (- and -) with a single bit line (- and -) per memory element. A TCAM cell () can also include a compare stack () and two word lines ( and ) that can connect to each memory element (- and -). The memory elements (- and -) can include SRAM type memory cells with one of two data terminals connected to a pre-write potential (Vpre, which can be a ground potential, or the like). Write operations can include pre-setting the data values of memory elements (- and -) to the pre-write potential prior to providing write data via the bit lines (- and -).

Content Addressable Memory (Cam) Cell Bit Line Architecture

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US Patent:
7307861, Dec 11, 2007
Filed:
Dec 28, 2006
Appl. No.:
11/647696
Inventors:
Roger Bettman - Los Altos CA, US
Eric H. Voelkel - Ben Lomond CA, US
Assignee:
Netlogic Microsystems, Inc. - Mountain View CA
International Classification:
G11C 15/00
G11C 11/00
G11C 7/10
G11C 7/06
G06F 12/00
US Classification:
365 49, 365154, 36518905, 36518907, 711108, 711117, 711118, 711128
Abstract:
A ternary content addressable memory (TCAM) cell () can include two memory elements (- and -) with a single bit line (- and -) per memory element. A TCAM cell () can also include a compare stack () and two word lines ( and ) that can connect to each memory element (- and -). The memory elements (- and -) can include SRAM type memory cells with one of two data terminals connected to a pre-write potential (Vpre, which can be a ground potential, or the like). Write operations can include pre-setting the data values of memory elements (- and -) to the pre-write potential prior to providing write data via the bit lines (- and -).
Roger Jay Bettman from Mountain View, CA, age ~73 Get Report