Roger P Ang

7350173, Mar 25, 2008

Jan 23, 2003

10/351094

Roger P. Ang - Cypress CA, US
Ken R. McElvain - Houston TX, US
Kenneth S. McElvain - Los Altos CA, US

Synplicity, Inc. - Sunnyvale CA

G06F 17/50

716 8, 716 9

Methods and apparatuses to place and route cells on integrated circuit chips along paths. In one aspect of the invention, methods to layout an integrated circuit are based on placing and routing cells along paths. In one embodiment, a method to layout an integrated circuit including: routing a wire to connect a first cell of the integrated circuit and a second cell of the integrated circuit; and placing a third cell of the integrated circuit after the wire is routed to connect the first cell and the second cell. In one example, the first, second and third cells are on a first path; and, the third cell is connected to one of the first and second cells on the first path by only one net. The first path is selected from a set of paths; and the first and second cells are placed before the wire is routed to connect the first cell and the second cell. Timing is analyzed using a route of the wire connecting the first cell and the second cell to select a second path from the set of paths before a cell is placed on the second path.

20080201678, Aug 21, 2008

Feb 7, 2008

12/069206

Roger P. Ang - Cypress CA, US
Ken R. McElvain - Houston TX, US
Kenneth S. McElvain - Los Altos CA, US

G06F 17/50

716 8

Methods and apparatuses to place and route cells on integrated circuit chips along paths. In one aspect of the invention, methods to layout an integrated circuit are based on placing and routing cells along paths. In one embodiment, a method to layout an integrated circuit including: routing a wire to connect a first cell of the integrated circuit and a second cell of the integrated circuit; and placing a third cell of the integrated circuit after the wire is routed to connect the first cell and the second cell. In one example, the first, second and third cells are on a first path; and, the third cell is connected to one of the first and second cells on the first path by only one net. The first path is selected from a set of paths; and the first and second cells are placed before the wire is routed to connect the first cell and the second cell. Timing is analyzed using a route of the wire connecting the first cell and the second cell to select a second path from the set of paths before a cell is placed on the second path.

6519753, Feb 11, 2003

Nov 30, 1999

09/451681

Roger Ang - Fremont CA
Atul Ahuja - Mountain View CA
Mukesh T. Lulla - Fremont CA
Drazen Borkovic - Mountain View CA
Brian D. Small - Portland OR
Charles C. Tralka - San Jose CA
Andrew K. Chan - Palo Alto CA
Kevin K. Yee - San Jose CA

QuickLogic Corporation - Sunnyvale CA

G06F 1750

716 16

A programmable device, such as a field programmable gate array, includes a main field that is programmable by the user and at least one embedded portion that is reserved to be programmed with a standard circuit design that is configured, for example, by the manufacturer. The embedded portion is similar to the main field, i. e. , it has the same programmable structure, however, the embedded portion is not accessible to the user. In some embodiments, the embedded portion may be pre-programmed with the standard circuit design and in other embodiments the embedded portion is programmed while the user programs the main field. The programmable device may also include signature bits that are used by the programming unit to identify the programmable device as having the embedded portion and which standard circuit design to program into the embedded portion. The signature bit may be programmed after the manufacture of the programmable device or may be hard wired during the manufacture of the device. The programming unit recognizes the configuration of the signature bits and restricts access to embedded portion based on the configuration.