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Rocco Robortaccio Phones & Addresses

  • 11 Ridgeview Rd, Hopewell Jct, NY 12533 (845) 227-5554
  • Ridgeview Rd, Hopewell Junction, NY 12533
  • Hopewell, NY

Publications

Us Patents

Bi-Directional Transceiver Circuit

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US Patent:
46988009, Oct 6, 1987
Filed:
Oct 28, 1985
Appl. No.:
6/792267
Inventors:
Joseph R. Cavaliere - Hopewell Junction NY
Albert Y. Chang - Poughkeepsie NY
Rocco J. Robortaccio - Hopewell Junction NY
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H04B 900
US Classification:
370 24
Abstract:
A simultaneous bi-directional transceiver is described. The transceiver comprises two circuits which are disposed at opposite ends of an interchip cable. In response to the application of digital data signals to these circuits, they generate a trilevel voltage at the ends of the interchip cable. Then, in each circuit, a first input to a differential amplifier is generated from the trilevel voltage by a level shifter comprising a first diode and a first constant current sink and a second input to the differential amplifier is derived from the digital data input signal applied to that circuit by a level shifter comprising a second diode and a second constant current source. Finally, the transceiver outputs are generated from the differential amplifier outputs.

Testing Embedded Arrays

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US Patent:
39612546, Jun 1, 1976
Filed:
Dec 20, 1974
Appl. No.:
5/534608
Inventors:
Joseph R. Cavaliere - Hopewell Junction NY
Rocco Robortaccio - Hopewell Junction NY
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G01R 1512
US Classification:
324 73AT
Abstract:
An LSI semiconductor device includes a memory array incorporating address, data and buffer registers, and associated combinatorial and/or sequential logic circuitry. The array is "embedded" in the sense that the memory array is not directly accessible, either in whole or in part, from the input and output terminals or pads of the device. To facilitate testing, means which bypass the associated logic circuitry are provided for scanning information directly into the address and data registers. The information so introduced is shifted through the register strings. The interconnections from the associated logic circuitry are inhibited during the testing mode while the information shifting means are inhibited during an operative mode. The information scanned into the registers may be scanned out to determine whether there is a defect or problem in the register strings. Output levels from the array are compared with an expected output.

Ttl Logic Circuit Employing Feedback To Improved The Speed-Power Curve

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US Patent:
45217009, Jun 4, 1985
Filed:
Dec 23, 1982
Appl. No.:
6/452541
Inventors:
Richard J. Blumberg - Poughkeepsie NY
Stewart Brenner - Wappingers Falls NY
Rocco J. Robortaccio - Hopewell Junction NY
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H03K 19003
H03K 19088
US Classification:
307456
Abstract:
Disclosed is the addition of passive feedback to a prior art T. sup. 2 L circuit. The T. sup. 2 L circuit with feedback, in accordance with the invention, has a lower power dissipation while retaining noise immunity and small gate delay. The additional resistor required for the feedback T. sup. 2 L circuit, in accordance with the invention, can be incorporated into the T. sup. 2 L cell without increasing the cell size. The feedback T. sup. 2 L circuit, in accordance with the invention, lends itself to the addition of an integrated direct-coupled inverter (DCI) function. The feedback T. sup. 2 L circuit, in accordance with the invention, permits more function to be placed on an integrated circuit semiconductor chip while maintaining gate performance and adherence to power restrictions.
Rocco J Robortaccio from Hopewell Junction, NY, age ~83 Get Report