Robert Melberg Phones & Addresses
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5000 Monroe Ave, Bemidji, MN 56601 (218) 755-1200
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2015 Anne St, Bemidji, MN 56601 (218) 759-2749
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3019 W 74Th St, Minneapolis, MN 55423 (612) 861-4990
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Richfield, MN
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Saint Francis, MN
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Andover, MN
Publications
Us Patents
Integrating Processor Element
View pageUS Patent:
41842014, Jan 15, 1980
Filed:
Apr 26, 1978
Appl. No.:
5/899909
Inventors:
Robert A. Melberg - Bloomington MN
Richard J. Wagner - West St. Paul MN
Richard J. Wagner - West St. Paul MN
Assignee:
Sperry Rand Corporation - New York NY
International Classification:
G06F 100
US Classification:
364200
Abstract:
An integrating processor element containing a data processor that provides a computer with those functions normally associated with the Central Processor Unit (CPU) but which possesses architectural features to prevent compromise (i. e. , unauthorized dissemination) of data in a multi-level secure environment. The data processor executes instructions from an internal instruction memory which cannot be altered by the data processor and cannot be accessed by the I/O processor (i. e. , I/O controller). The instruction memory is segmented providing a separate segment for each discrete level of secure data to be processed. Each computer program is stored in the segment corresponding to the highest level of security of the data it will use. A second memory, called the hand-off memory, is a read/write memory accessible by the I/O processor as well as the data processor. The hand-off memory is also segmented by security level.
Integrating I/O Element
View pageUS Patent:
41842006, Jan 15, 1980
Filed:
Apr 26, 1978
Appl. No.:
5/899908
Inventors:
Richard J. Wagner - West St. Paul MN
Robert A. Melberg - Bloomington MN
Robert A. Melberg - Bloomington MN
Assignee:
Sperry Rand Corporation - New York NY
International Classification:
G06F 100
US Classification:
364200
Abstract:
An integrating Input/Output (I/O) element containing an I/O processor that provides a computer with those functions normally associated with an I/O processor (or I/O controller) but which possesses architectural features to prevent compromise (i. e. , unauthorized dissemination) of data in a multi-level secure environment. The I/O processor is programmable via an internal instruction memory which cannot be altered by the I/O processor and which cannot be accessed by any other portion of the computer (i. e. , Central Processor Unit). The instruction memory is segmented providing a separate segment for each I/O channel. The instructions used to control each I/O channel are stored within the segment of instruction memory allocated to that I/O channel. A secondary memory, called the hand-off memory, is a read/write memory accessible by the Central Processor Unit (CPU) as well as the I/O processor. The hand-off memory is also segmented having a separate segment for each level of secure data to be stored within the hand-off memory.