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Robert J Giggi

from Natick, MA
Age ~96

Robert Giggi Phones & Addresses

  • 119 Hartford St, Natick, MA 01760
  • Westwood, MA
  • Annapolis, MD
  • Bass River, MA
  • S Yarmouth, MA

Business Records

Name / Title
Company / Classification
Phones & Addresses
Robert W. Giggi
Pastor
St Linus Church
Church
119 Hartford St, Natick, MA 01760

Publications

Us Patents

Interface For Serial Data Communications Link

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US Patent:
44505728, May 22, 1984
Filed:
May 7, 1982
Appl. No.:
6/376069
Inventors:
Robert E. Stewart - Stow MA
John E. Buzynski - Windham NH
Robert Giggi - Merrimack NH
Assignee:
Digital Equipment Corporation - Maynard MA
International Classification:
H03K 513
US Classification:
375 87
Abstract:
An interface circuit (10) for coupling a parallel data device (12) to a serial data channel (14, 16) over which Manchester-type codes are transmitted. In the interface circuit, an efficient and reliable Manchester decoder (22), comprising a flip-flop (50), an exclusive-or gate (52), and at least one delay line (58A or 58B) separates the data and clocking signals. The serial data signals are clocked into a serial register (30) under control of the external clocking signals from the channel. A carrier detector (24) enables the serial register only when valid information signals are present. A parallel data register (40) receives in parallel the data from the serial data register. To get in phase the external clocking signals with the internal clock source, an internal clock synchronizing circuit (34, 42) recycles the internal clock source upon the occurrence of a synchronizing character that is transmitted over the serial data channel. In this fashion, the internal operations of the parallel data transfers are in phase, but isolated from the external clocking signals so that in the event that the external clocking signals become corrupted due to noise or simultaneous transmissions of information signals by different devices, the internal parallel transfer operations may continue freely without disruption.

Memory Module With Selectable Byte Addressing For Digital Data Processing System

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US Patent:
40457818, Aug 30, 1977
Filed:
Feb 13, 1976
Appl. No.:
5/658071
Inventors:
John V. Levy - Harvard MA
Thomas A. Northrup - Westford MA
Robert Giggi - Peabody MA
Assignee:
Digital Equipment Corporation - Maynard MA
International Classification:
G06F 910
US Classification:
364200
Abstract:
A memory arrangement for a digital data processing system that includes a high-speed associative memory unit and a random access back-up unit. The associative memory unit contains a multiple location address memory and a multiple location data memory wherein there is a correspondence between each address location and a data location. Each time a central processor initiates a reading operation, it issues an address to define a data location. If the associative memory unit contains that address at a location in its address memory, it performs a reading memory cycle and transfers data from the corresponding location in the data memory directly to the central processor. If the data is not available in the associative memory unit during a reading operation, or if the central processor is transferring data to the address location during a writing operation, the associative memory unit causes the back-up unit to perform a corresponding memory cycle. If the address memory in the associative memory unit contains a corresponding address, the new data also is transferred to the corresponding location in the data memory. Secondary memory units, such as disk memory units, and input/output units also communicate with the back-up memory unit and the associative memory unit.

Cached Multiprocessor System With Pipeline Timing

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US Patent:
43922007, Jul 5, 1983
Filed:
Feb 27, 1981
Appl. No.:
6/239129
Inventors:
Jega A. Arulpragasam - Stow MA
Robert A. Giggi - Merrimack NH
Richard F. Lary - Colorado Springs CO
Daniel T. Sullivan - Bolton MA
Assignee:
Digital Equipment Corporation - Maynard MA
International Classification:
G06F 910
US Classification:
364200
Abstract:
A multiprocessor data processing system, the processors (30) and input/output devices (32) of which share a common control unit (CCU 10) that includes a write-through cache memory (20), a memory management circuit (22) and an address translation circuit (24). The data processing system further includes random access memory (28) and a secondary storage facility (40, 42, 68, 70). The processors (30) and the input/output devices (32) use the memory management circuit (22), the address translation circuit (24) and the cache memory (20) in an ordered pipelined sequence. When a read command "misses" the cache memory (20), the CCU accesses the memory modules (28) for allocating its cache memory (20) and for returning read data to the processors (30) or input/output devices (32). The CCU also includes a duplicate tag store (67) that maintains a copy of the cache memory address tag store (20A) thereby to enable the CCU to update its cache memory when data is written into a memory location that is to be maintained in the cache memory.
Robert J Giggi from Natick, MA, age ~96 Get Report