Ritu E Shrivastava from 44455 Parkmeadow Dr, Fremont, CA 94539, age 74, Phone: (510) 659-8062

Dram Cell Having Storage Capacitor Contact Self-Aligned To Bit Lines And Word Lines

View page

US Patent:

6373089, Apr 16, 2002

Filed:

Aug 10, 2000

Appl. No.:

09/637322

Inventors:

Ritu Shrivastava - Fremont CA
Chitranjan N. Reddy - Los Altos Hills CA

Assignee:

Alliance Semiconductor Corporation - Santa Clara CA

International Classification:

H01L 27108

US Classification:

257306, 257296, 257649

Abstract:

A DRAM cell ( ) having a capacitor-over-bit line (COB) structure self-aligned to the word lines and bit lines is disclosed. Word lines ( ) and bit lines ( ) are formed with insulating structures that include insulating sidewalls. The word line insulating structure includes an etch barrier layer ( ) that extends over a source region ( ). A first interlayer dielectric (ILD) ( ) insulates the word lines ( ) from the bit lines ( ) and a second ILD ( ) insulates the bit lines from a cell capacitor. A capacitor contact hole ( ), self-aligned with the bit lines and the word lines, is formed by etching through the first and second ILDs ( and ) to expose the etch barrier layer ( ) over the source region ( ). Portions of the bit line and word line exposed by the etch are protected by their respective insulating structures. The exposed etch barrier layer ( ) over the source region ( ) is cleared and a storage capacitor is formed having a contact that extends into the contact hole to make contact with the source region ( ).

Flash Eprom Array With Self-Aligned Source Contacts And Programmable Sector Erase Architecture

View page

US Patent:

6392267, May 21, 2002

Filed:

Apr 25, 1997

Appl. No.:

08/845752

Inventors:

Ritu Shrivastava - Fremont CA
Chitranjan N. Reddy - Los Altos Hills CA

Assignee:

Alliance Semiconductor Corporation - Santa Clara CA

International Classification:

H01L 29788

US Classification:

257316, 257322

Abstract:

A flash EPROM array ( ) and method of manufacture is disclosed. Source regions ( ) are shared between the memory cells ( ) of row ( ) pairs, and are isolated from one another in the row direction by isolation regions. Low resistance source conductor members ( ) extend in the row direction and are formed over the source regions ( ) and make contact therewith in a self-aligned fashion. The architecture allows for source decoding and thus enables user programmable sector erase architecture.

Flash Eprom Memory Cell Having Increased Capacitive Coupling And Method Of Manufacture Thereof

View page

US Patent:

6429076, Aug 6, 2002

Filed:

Jan 22, 2001

Appl. No.:

09/766971

Inventors:

Perumal Ratnam - Fremont CA
Ritu Shrivastava - Fremont CA

Assignee:

Alliance Semiconductor Corporation - Santa Clara CA

International Classification:

H01L 218247

US Classification:

438264

Abstract:

A flash EPROM cell ( ) is disclosed having increased capacitive coupling between a floating gate ( ) and a control gate ( ). Vertical structural elements ( and ) are formed on field oxide regions ( ) on opposing sides of the flash EPROM cell channel , in the channel width direction. The structural elements ( and ) include relatively vertical faces. The floating gate ( ) conformally cover the channel and the vertical faces of the structural elements ( and ). The control gate ( ) conformally covers the floating gate ( ). The vertical displacement introduced by the structural elements ( and ) increases the overlap area between the floating gate ( ) and the control gate ( ) without increasing the overlap area of the floating gate ( ) and the channel , resulting in increased capacitive coupling between the control gate ( ) and the floating gate ( ). A process is disclosed which enables the formation of the above structural elements ( and ) with dimensions that are smaller than those normally achievable by the minimum resolution of lithography equipment.

Dram Cell Having Storage Capacitor Contact Self-Aligned To Bit Lines And Word Lines

View page

US Patent:

6472267, Oct 29, 2002

Filed:

Dec 3, 2001

Appl. No.:

10/007110

Inventors:

Ritu Shrivastava - Fremont CA
Chitranjan N. Reddy - Los Altos Hills CA

Assignee:

Alliance Semiconductor Corporation - Santa Clara CA

International Classification:

H01L 218242

US Classification:

438244, 438253, 438396, 257306

Abstract:

A DRAM cell ( ) having a capacitor-over-bit line (COB) structure self-aligned to the word lines and bit lines is disclosed. Word lines ( ) and bit lines ( ) are formed with insulating structures that include insulating sidewalls. The word line insulating structure includes an etch barrier layer ( ) that extends over a source region ( ). A first interlayer dielectric (ILD) ( ) insulates the word lines ( ) from the bit lines ( ) and a second ILD ( ) insulates the bit lines from a cell capacitor. A capacitor contact hole ( ), self-aligned with the bit lines and the word lines, is formed by etching through the first and second ILDs ( and ) to expose the etch barrier layer ( ) over the source region ( ). Portions of the bit line and word line exposed by the etch are protected by their respective insulating structures. The exposed etch barrier layer ( ) over the source region ( ) is cleared and a storage capacitor is formed having a contact that extends into the contact hole to make contact with the source region ( ).

Semiconductor Chip That Isolates Dram Cells From The Peripheral Circuitry And Reduces The Cell Leakage Current

View page

US Patent:

6589834, Jul 8, 2003

Filed:

May 3, 2001

Appl. No.:

09/848627

Inventors:

Chitranjan N. Reddy - Los Alto Hills CA
Ritu Shrivastava - Fremont CA

Assignee:

Alliance Semiconductor Corporation - Santa Clara CA

International Classification:

H01L 218238

US Classification:

438210, 438220, 438224, 438228, 438241, 438276, 438414

Abstract:

The dynamic random access memory (DRAM) cells in a semiconductor chip are isolated from the peripheral circuitry by forming the DRAM cells directly in the substrate while the peripheral and other functional circuits are formed in wells that are isolated from the substrate. In addition to providing isolation, the placement of the DRAM cells also reduces the leakage current in the cells, thereby increasing the time that a DRAM cell can hold a charge without being refreshed.

Method And Apparatus For Integrating Flash Eprom And Sram Cells On A Common Substrate

View page

US Patent:

6903434, Jun 7, 2005

Filed:

May 20, 1999

Appl. No.:

09/315599

Inventors:

Ritu Shrivastava - Fremont CA, US

Assignee:

Alliance Semiconductors - Santa Clara CA

International Classification:

H01L029/00

US Classification:

257499, 257501, 257502, 257511

Abstract:

A system for and a method of integrating SRAM cells and flash EPROM cells onto a single silicon substrate includes an area on the silicon substrate where a local oxidation of silicon (LOCOS) isolation technique is implemented and another area on the same silicon substrate where a shallow trench isolation (STI) technique is implemented. Further, this system and method also include flash EPROM cells implemented within the area of the substrate utilizing the LOCOS isolation technique and SRAM cells implemented within the area of the substrate utilizing the STI technique. Preferably, the LOCOS isolation technique is first implemented to define a flash area of the silicon substrate on which the flash EPROM cell is implemented. Before the LOCOS isolation technique is implemented, an SRAM area is masked. After the LOCOS isolation technique has been fully implemented, the flash area is then preferably masked and the STI technique is implemented in order to define the SRAM area of the silicon substrate on which the SRAM cell is implemented.

Method Of And Apparatus For Integrating Flash Eprom And Sram Cells On A Common Substrate

View page

US Patent:

6921688, Jul 26, 2005

Filed:

Mar 7, 2003

Appl. No.:

10/383971

Inventors:

Ritu Shrivastava - Fremont CA, US

Assignee:

Alliance Semiconductor - San Jose CA

International Classification:

H01L021/8238

US Classification:

438207, 438218, 438219, 438284

Abstract:

A system for and a method of integrating SRAM cells and flash EPROM cells onto a single silicon substrate includes an area on the silicon substrate where a local oxidation of silicon (LOCOS) isolation technique is implemented and another area on the same silicon substrate where a shallow trench isolation (STI) technique is implemented. Further, this system and method also include flash EPROM cells implemented within the area of the substrate utilizing the LOCOS isolation technique and SRAM cells implemented within the area of the substrate utilizing the STI technique. Preferably, the LOCOS isolation technique is first implemented to define a flash area of the silicon substrate on which the flash EPROM cell is implemented. Before the LOCOS isolation technique is implemented, an SRAM area is masked. After the LOCOS isolation technique has been fully implemented, the flash area is then preferably masked and the STI technique is implemented in order to define the SRAM area of the silicon substrate on which the SRAM cell is implemented.

Processing Systems And Methods For Molecular Memory

View page

US Patent:

7358113, Apr 15, 2008

Filed:

Apr 29, 2005

Appl. No.:

11/118042

Inventors:

Ritu Shrivastava - Fremont CA, US
Antonio R. Gallo - Colorado Springs CO, US
Kenneth J. Mobley - Colorado Springs CO, US
Tom DeBolske - Santa Cruz CA, US

Assignee:

Zettacore, Inc. - Englewood CO

International Classification:

H01L 51/40

US Classification:

438 99, 257E51023

Abstract:

Molecular memories, i. e. , memories that incorporate molecules for charge storage, are disclosed. Molecular memory cells, molecular memory arrays, and electronic devices including molecular memory are also disclosed, as are processing systems and methods for manufacturing molecular memories. Methods of manufacturing molecular memories that enable semiconductor devices and interconnections to be manufactured monolithically with molecular memory are also disclosed.