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Ridvan Amir Sahan

from Sunnyvale, CA
Age ~57

Ridvan Sahan Phones & Addresses

  • 1131 Pome Ave, Sunnyvale, CA 94087 (408) 833-9706
  • 794 Grape Ave, Sunnyvale, CA 94087 (408) 749-1573
  • 676 Bellflower Ave, Sunnyvale, CA 94086 (408) 749-1573
  • 1947 Hillcrest Ave, Bethlehem, PA 18018 (610) 954-8343
  • 3255 Kifer Rd, Santa Clara, CA 95051
  • San Jose, CA
  • Oak Creek, CO
  • Lebanon, NH
  • Mountain View, CA
  • 1131 Pome Ave, Sunnyvale, CA 94087 (408) 749-1573

Work

Company: Fluent inc. Aug 1999 to Jan 2006 Position: Senior technical support engineer

Education

School / High School: Lehigh University 1990 to 1997

Skills

Simulations • Cfd • Finite Element Analysis • Ansys • Mechanical Engineering • Design of Experiments • Matlab • Engineering • Algorithms • Electronics • Heat Transfer • Thermal • Thermodynamics • Fluid Mechanics • Thermal Analysis • Labview

Languages

English

Interests

Exercise • Home Improvement • Reading • Sports • Cooking • Cruises • Electronics • Sewing • Crafts • Fitness • Music • Dogs • Movies • Kids • Diet • Walking • Travel • Investing • Traveling

Industries

Mechanical Or Industrial Engineering

Resumes

Resumes

Ridvan Sahan Photo 1

Staff Thermal Design Engineer

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Location:
1131 Pome Ave, Sunnyvale, CA 94087
Industry:
Mechanical Or Industrial Engineering
Work:
Fluent Inc. Aug 1999 - Jan 2006
Senior Technical Support Engineer

Intel Corporation Aug 1999 - Jan 2006
Staff Thermal Design Engineer
Education:
Lehigh University 1990 - 1997
Istanbul Technical University 1984 - 1988
Bachelors, Bachelor of Science, Mechanical Engineering
Skills:
Simulations
Cfd
Finite Element Analysis
Ansys
Mechanical Engineering
Design of Experiments
Matlab
Engineering
Algorithms
Electronics
Heat Transfer
Thermal
Thermodynamics
Fluid Mechanics
Thermal Analysis
Labview
Interests:
Exercise
Home Improvement
Reading
Sports
Cooking
Cruises
Electronics
Sewing
Crafts
Fitness
Music
Dogs
Movies
Kids
Diet
Walking
Travel
Investing
Traveling
Languages:
English

Publications

Us Patents

Quick Release Retention Mechanism For Socketed Microelectronic Devices

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US Patent:
20120156913, Jun 21, 2012
Filed:
Dec 17, 2010
Appl. No.:
12/972101
Inventors:
Aslam H. Haswarey - Portland OR, US
Mustafa H. Haswarey - Hillsboro OR, US
Ridvan A. Sahan - Sunnyvale CA, US
Rahima K. Mohammed - San Jose CA, US
International Classification:
H01R 13/62
H01R 43/26
US Classification:
439331, 439345, 29446
Abstract:
The present description relates to the field of microelectronic device retention mechanisms and, more particularly, to a quick release retention mechanism including a base plate, a load plate and a biasing mechanism adapted to apply a desired load and to allow rapid insertion and extraction of microelectronic devices from sockets.

Reconfigurable Cooling Assembly For Integrated Circuitry

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US Patent:
20200027808, Jan 23, 2020
Filed:
Sep 30, 2016
Appl. No.:
16/337883
Inventors:
- Santa Clara CA, US
Tong W. CHAO - San Jose CA, US
Stephanie L. SEAMAN - Hillsboro OR, US
Ridvan A. SAHAN - Sunnyvale CA, US
Ying-Feng PANG - San Jose CA, US
International Classification:
H01L 23/36
H05K 7/20
H01L 23/427
Abstract:
Reconfigurable cooling assemblies for thermal management of integrated circuitry are provided. Such assemblies can be modular and can permit or otherwise facilitate scalable thermal performance with respect to power dissipation demands. In some embodiments, a reconfigurable modular cooling assembly can be reversibly configured to adjust reversibly the cooling capacity of the assembly for a defined power dissipation requirement. A form factor of a reconfigurable modular cooling assembly can be based at least on the defined power dissipation requirement. In some embodiments, a reconfigurable modular cooling assembly can include a pedestal member and multiple attachment members that can be reversibly coupled to or reversibly decoupled from the pedestal based at least on a power dissipation condition and/or a change thereof in a dissipative electronic component included in a semiconductor package. Scalability of thermal performance of the reconfigurable modular cooling assembly can be achieved, at least in part, by the addition of attachment members.

Test, Validation, And Debug Architecture

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US Patent:
20150127983, May 7, 2015
Filed:
Dec 23, 2010
Appl. No.:
13/997182
Inventors:
Mark B. Trobough - Olympia WA, US
Keshavan K. Tiruvallur - Tigard OR, US
Chinna B. Prudvi - Portland OR, US
Christian E. Iovin - Federal Way WA, US
David W. Grawrock - Aloha OR, US
Jay J. Nejedlo - Wilsonville OR, US
Ashok N. Kabadi - Portland OR, US
Travis K. Goff - Hillsboro OR, US
Evan J. Halprin - Hillsboro OR, US
Kapila B. Udawatta - San Diego CA, US
Jiun Long Foo - Bayan Lepas, MY
Wee Hoo Cheah - Bayan Lepas, MY
Vui Yong Liew - Bukit Mertajam, MY
Selvakumar Raja Gopal - Tapah, MY
Yuen Tat Lee - Bayan Lepas, MY
Samie B. Samaan - West Linn OR, US
Kip C. Killpack - Beaverton OR, US
Neil Dobler - Aloha OR, US
Nagib Z. Hakim - Santa Clara CA, US
Briar Meyer - Cornelius OR, US
William H. Penner - Olympia WA, US
John L. Baudrexl - Olympia WA, US
Russell J. Wunderlich - Livermore CO, US
James J. Grealish - Beaverton OR, US
Kyle Markley - Hillsboro OR, US
Timothy S. Storey - Hillsboro OR, US
Loren J. McConnell - Forest Grove OR, US
Lyle E. Cool - Beaverton OR, US
Mukesh Kataria - Fremont CA, US
Rahima K. Mohammed - San Jose CA, US
Tieyu Zheng - Sammamish WA, US
Yi Amy Xia - Campbell CA, US
Ridvan A. Sahan - Sunnyvale CA, US
Arun R. Ramadorai - Sammamish WA, US
Priyadarsan Patra - Austin TX, US
Edwin E. Parks - Hillsboro OR, US
Abhijit Davare - Hillsboro OR, US
Padmakumar Gopal - Austin TX, US
Bruce Querbach - Beaverton OR, US
Hermann W. Gartler - Portland OR, US
Keith Drescher - Olympia WA, US
Sanjay S. Salem - Portland OR, US
David C. Florey - Hillsboro OR, US
Assignee:
INTEL CORPORATION - Santa Clara CA
International Classification:
G06F 11/273
US Classification:
714 30
Abstract:
An apparatus and method is described herein for providing a test, validation, and debug architecture. At a target or base level, hardware (Design for Test or DFx) are designed into and integrated with silicon parts. A controller may provide abstracted access to such hooks, such as through an abstraction layer that abstracts low level details of the hardware DFx. In addition, the abstraction layer through an interface, such as APIs, provides services, routines, and data structures to higher-level software/presentation layers, which are able to collect test data for validation and debug of a unit/platform under test. Moreover, the architecture potentially provides tiered (multiple levels of) secure access to the test architecture. Additionally, physical access to the test architecture for a platform may be simplified through use of a unified, bi-directional test access port, while also potentially allowing remote access to perform remote test and de-bug of a part/platform under test. In essence, a complete test architecture stack is described herein for test, validation, and debug of electronic parts, devices, and platforms.
Ridvan Amir Sahan from Sunnyvale, CA, age ~57 Get Report