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Richard A Summe

from Greensboro, NC
Age ~65
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Also known as:
Richard Augustine Summe
Phone and address:
2217 Brigham Rd, Greensboro, NC 27409
(336) 662-9238
Related to:
Jennifer M Summe, 42Stephanie Summe, 33Jennifer Summe Towler, 42Jenny Summe, 42Spencer J Towler, 37James J Haas, 62S SummeColleen E Summe, 41Arthur C Towler, 32S Summe, 33Michael A Summe, 44Kimberly A Summe, 54Jennifer SummeAchristian TowlerColleen O Summe, 40Jerilyn M Summe, 63Lisa M Summe, 58
Connected to:
Amy J Summe, 49Carl Summe, 52Gabrielle A Summe, 58Kathleen S Summe, 66Aubrey E Summerall, 48Becky A Summer, 70Brenda W Summer, 79Charlene Summerall, 45Chelsea Summer, 54Craig A Summerall, 51

Richard Summe Phones & Addresses

  • 2217 Brigham Rd, Greensboro, NC 27409 (336) 662-9238
  • Guilford, NC
  • Highland Village, TX
  • 608 Venetian Way, Kokomo, IN 46901 (336) 662-9238
  • Irving, TX
  • 2217 Brigham Rd, Greensboro, NC 27409 (910) 425-1819

Work

Company: Triquint semiconductor Nov 2012 Position: Senior analog design engineer

Education

Degree: Master of Science (MS) School / High School: Purdue University Specialities: Electrical and Electronics Engineering

Skills

Mixed Signal • Rf • Analog Circuit Design • Semiconductors • Ic • Circuit Design • Pll • Analog • Cmos • Wireless • Rf Design

Industries

Wireless

Resumes

Resumes

Richard Summe Photo 1

Senior Analog Design Engineer

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Location:
Greensboro, NC
Industry:
Wireless
Work:
TriQuint Semiconductor since Nov 2012
Senior Analog Design Engineer
Orthoradio - Greensboro/Winston-Salem, North Carolina Area Jul 2008 - Aug 2012
Principal Mixed Signal Design Engineer
RFMD, Inc. 2000 - 2008
Principal Mixed Signal IC Design Engineer
STMicroelectronics 1996 - 2000
analog design manager
Education:
Purdue University
Master of Science (MS), Electrical and Electronics Engineering University of Cincinnati
MS, Electrical and Electronics Engineering
Skills:
Mixed Signal
Rf
Analog Circuit Design
Semiconductors
Ic
Circuit Design
Pll
Analog
Cmos
Wireless
Rf Design

Publications

Us Patents

Phase Dithered Digital Communications System

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US Patent:
8068573, Nov 29, 2011
Filed:
Apr 27, 2007
Appl. No.:
11/740967
Inventors:
Nadim Khlat - Midi-Pyrenees, FR
Richard A. Summe - Greensboro NC, US
Scott Robert Humphreys - Greensboro NC, US
Chris Ngo - Chandler AZ, US
Assignee:
RF Micro Devices, Inc. - Greensboro NC
International Classification:
H04L 7/00
H03L 7/00
US Classification:
375355, 327141, 375354
Abstract:
The present invention is a phase dithered digital communications system that includes a digital receiver, and uses phase dithering to spread the energy of one or more system clocks to minimize receiver de-sensitization. Phase dithering uses a single frequency for each system clock; however, the energy of each system clock is spread over a range of frequencies by changing the duty-cycle of each clock half-cycle. A non-phase dithered clock drives the sampling clock of a receiver analog-to-digital converter to provide accurate correlation with received information, which may allow use of a higher frequency sampling clock than in frequency dithered designs. Phase dithered clocks and non-phase dithered clocks may have constant frequencies that are related to each other by a ratio of two integers; therefore, the time base used for extracting received data is always correlated and accurate.

Method Of Making A High Voltage Implanted Channel Device For Vlsi And Ulsi Processes

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US Patent:
53669169, Nov 22, 1994
Filed:
Feb 4, 1993
Appl. No.:
8/013947
Inventors:
Richard A. Summe - Kokomo IN
Randy A. Rusch - Kokomo IN
Douglas R. Schnabel - Kokomo IN
Jack D. Parrish - Kokomo IN
Assignee:
Delco Electronics Corporation - Kokomo IN
International Classification:
H01L 21265
US Classification:
437 44
Abstract:
A process for fabricating a high voltage CMOS transistor having a non-self aligned implanted channel which permits the operation of the device at high voltages. The non-self aligned implanted channel does not require alignment with the gate electrode of the CMOS device, but is accurately implanted early in the fabrication of the device through reliance on direct wafer stepper technology. As a result, the non-self aligned implanted channel does not require a high temperature drive, such that fabrication of the transistor is compatible with VLSI and ULSI processes, and the transistor can be up-integrated onto logic integrated circuits. Accuracy of the placement of the non-self aligned implanted channel provides for a shorter channel length, which enables the device to be highly area efficient while also increasing the current capability of the device. Furthermore, the transistor is characterized by a large field-induced avalanche breakdown voltage, enhanced by a thick gate oxide, a lightly doped drain, a field oxide region between the gate and the drain, and known field plating techniques.

Current Limit Circuit

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US Patent:
52891097, Feb 22, 1994
Filed:
Mar 5, 1990
Appl. No.:
7/488160
Inventors:
Richard A. Summe - Kokomo IN
Assignee:
Delco Electronics Corporation - Kokomo IN
International Classification:
G05F 1573
US Classification:
323277
Abstract:
A current limit circuit for limiting current flow through a load circuit. The amount of current flowing in the circuit is sensed by a current sensing resistor. The circuit includes a P-channel field effect transistor and an NPN bipolar transistor. When current sensed by the resistor attains a current limit value, the field effect transistor is turned on and its output current is amplified by the NPN transistor. The emitter of the NPN transistor is connected to the gate of another P-channel field effect transistor which is connected to the load circuit.

Low Noise Communication Bus Driver

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US Patent:
51646110, Nov 17, 1992
Filed:
Oct 18, 1990
Appl. No.:
7/599532
Inventors:
Richard A. Summe - Kokomo IN
Assignee:
Delco Electronics Corporation - Kokomo IN
International Classification:
H03K 500
H03K 512
H06F 7566
G06G 724
US Classification:
307261
Abstract:
This invention relates to a waveshaping circuit for producing a bus output voltage signal having a substantially sinusoidal rising transition from a low voltage level to a high voltage level in response to the rising edge of a data input signal, and a substantially sinusoidal falling transition from said high voltage level to said low voltage level, in response to the falling edge of said data input signal. The circuit uses AC coupling to control the waveshaping. This allows the circuit to operate with a large ground offset voltage difference between circuit ground and bus ground. An exponential current source provides a current to a regulator bus driver which charges and discharges a capacitor in response to the the rising edge or falling edge on the data input signal. The current increases exponentially in response to the rising or falling edge on the data input signal and then decreasing exponentially when the bus output signal reaches one-half of its intended full voltage swing or falls below one-half the full voltage swing to respectively produce the sinusoidal rising and falling voltage at the bus output. The regulator bus driver regulates the voltage at the bus output when the voltage reaches the intended full voltage.

Fast Locking Phase Locked Loop Frequency Synthesizer

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US Patent:
53845510, Jan 24, 1995
Filed:
Feb 25, 1993
Appl. No.:
8/023795
Inventors:
Richard A. Kennedy - Kokomo IN
Richard A. Summe - Kokomo IN
John R. Pacourek - Oak Creek WI
Assignee:
Delco Electronics Corporation - Kokomo IN
International Classification:
H03L 7089
H03L 7093
H03L 7107
H03L 718
US Classification:
331 17
Abstract:
A radio apparatus with a phase locked loop is disclosed. The apparatus contains a phase detector with first and second inputs, where the first input receiving a reference frequency signal and the second input receives a controllable frequency signal that is controlled by a tuning voltage. Also included is, a loop filter for filtering the output of the phase detector, circuitry for decoding when a phase difference at the inputs of the phase detector exceeds a predetermined value, and a filter bypass circuit. This circuit bypasses operation of the loop filter when the difference at the inputs of the phase detector exceeds a predetermined value, allowing fast voltage changes of the tuning voltage, and providing a short lock time for the phase locked loop.

Isbn (Books And Publications)

IBM's Personal Computer

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Author

Richard Summe

ISBN #

0880221003

IBM's Personal Computer

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Author

Richard Summe

ISBN #

0880221011

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Richard A Summe from Greensboro, NC, age ~65 Get Report