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Richard E Serton

from Charlottesville, VA
Age ~45
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Also known as:
Richard Seeton
Phone and address:
307 18Th St NE, Charlottesville, VA 22902
(434) 979-4299
Related to:
Phyllis Levitt Feldman, 81Bernadette Serton
Connected to:
Alem Sertse, 46Martin W Sertterh, 71Thierry A Sertyn, 57Ana R Seru, 54Robin Seru, 56Analiese A Seruby, 33Allan Seruchar, 42Maria Serulle, 51Paula M Serum, 60Deidra L Serumgard, 43

Richard Serton Phones & Addresses

  • 307 18Th St NE, Charlottesvle, VA 22902 (434) 979-4299
  • Charlottesville, VA
  • 5 Falmouth Ct, Brookfield, CT 06804 (203) 740-4432
  • 4353 Staffordshire Ln, Fairfax, VA 22030 (703) 978-1059
  • Clinton, NY
  • 114 Canner St, New Haven, CT 06511 (203) 891-6361
  • White Plains, NY
  • New York, NY
  • Great Falls, VA
  • Poughkeepsie, NY
  • 4353 Staffordshire Ln, Fairfax, VA 22030 (315) 381-3213

Work

Company: Ibm corporation Jul 2001 Position: Advisory circuit design engineer

Education

School / High School: Columbia University School of Engineering and Applied Science Aug 1997 Specialities: Bachelor of Science in Computer Engineering

Skills

Cadence Virtuoso XL design suite • SKILL programming • VHDL • schematic capture • Calibre PDV suite • multi-pattern technology design • 3D FinFET design • IC floorplanning • circuit abstraction • Powerspice circuit analysis • power takedown • transistor-level timing takedown (STA) • electromigration analysis • design for manufacture (DFM) • standard cell library creation & adm... • UNIX/Windows/Mac OS • Perl scripting

Resumes

Resumes

Richard Serton Photo 1

Richard Serton Fairfax, VA

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Work:
IBM Corporation

Jul 2001 to 2000
Advisory Circuit Design Engineer
Education:
Columbia University School of Engineering and Applied Science
Aug 1997 to May 2001
Bachelor of Science in Computer Engineering
Skills:
Cadence Virtuoso XL design suite, SKILL programming, VHDL, schematic capture, Calibre PDV suite, multi-pattern technology design, 3D FinFET design, IC floorplanning, circuit abstraction, Powerspice circuit analysis, power takedown, transistor-level timing takedown (STA), electromigration analysis, design for manufacture (DFM), standard cell library creation & administration, UNIX/Windows/Mac OS, Perl scripting

Publications

Us Patents

Programmable Control Clock Circuit Including Scan Mode

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US Patent:
8299833, Oct 30, 2012
Filed:
Jun 9, 2010
Appl. No.:
12/796970
Inventors:
Paul A. Bunce - Poughkeepsie NY, US
Yuen H. Chan - Poughkeepsie NY, US
John D. Davis - Maybrook NY, US
Richard E. Serton - Clinton NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H03K 3/017
US Classification:
327172, 327176, 327291
Abstract:
A programmable clock control circuit includes a base block configured to control operation of the programmable clock control circuit and a chop block configured to control the width of an output clock signal of the programmable clock control circuit. The circuit also includes a pulse width variation block providing a pulse width variation output to the base block, the base block output being variable to provide at least three different output pulse widths. The circuit also includes a launch clock delay block coupled to delay the output of the base block and a scan clock delay block to delay the output pulse and a selector that causes either the scan clock delay block or the launch clock delay block to be active based on a value of a scan gate signal.

Single Clock Dynamic Compare Circuit

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US Patent:
20110298500, Dec 8, 2011
Filed:
Jun 2, 2010
Appl. No.:
12/792475
Inventors:
Yuen H. Chan - Poughkeepsie NY, US
Antonio R. Pelella - Highland Falls NY, US
Richard E. Serton - Clinton NY, US
Arthur Tuminaro - Lagrangeville NY, US
Assignee:
INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY
International Classification:
H03K 5/00
US Classification:
327 97
Abstract:
A compare circuit for comparing a first data word with a second data word includes a plurality of sub-circuits, each having a two-bit static compare stage and a dynamic complex logic stage; a dynamic compare node responsive to respective outputs of the sub-circuits; and an output latch that captures a comparison result in accordance with a logic state of the dynamic compare node. In an exemplary embodiment, a local clock generator provides a single controlling clock signal for clocking the output latch, precharging of the dynamic compare node, and clocking of the dynamic complex logic stage of the sub-circuits.

Latch-Up Avoidance For Sea-Of-Gates

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US Patent:
20230062945, Mar 2, 2023
Filed:
Aug 25, 2021
Appl. No.:
17/411113
Inventors:
- Armonk NY, US
Ryan Michael Kruse - Williamson TX, US
Leon Sigal - Monsey NY, US
Richard Edward Serton - Charlottesville VA, US
Matthew Stephen Angyal - Stormville NY, US
Terence Hook - Jericho Center VT, US
Richard Andre Wachnik - Mount Kisco NY, US
International Classification:
G06F 30/394
H01L 27/02
Abstract:
Aspects of the invention include systems and methods for implementing a CMOS circuit design that uses a sea-of-gates fill methodology to provide latch-up avoidance. A non-limiting example computer-implemented method includes identifying a fill cell in the circuit design. The fill cell can include a power rail, a ground rail, and a field-effect transistor (FET) electrically coupled to the power rail through a via. The method can include disconnecting the via from the power rail and moving the via to a disconnected node in the fill cell. Moving the via decouples a source or drain of the fill cell from a well of the fill cell, preventing latch-up while maintaining via and metal shape density.

Selective Exposure Of Standard Cell Output Nets For Improved Routing Solutions

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US Patent:
20230047053, Feb 16, 2023
Filed:
Aug 16, 2021
Appl. No.:
17/403108
Inventors:
- Armonk NY, US
Richard Edward Serton - Charlottesville VA, US
International Classification:
G06F 30/394
G06F 30/392
Abstract:
Provided are embodiments for a computer-implemented method for routing standard cells of an integrated circuit. Embodiments include obtaining a layout of a plurality of standard cells for routing, and determining existing output connections for each of the plurality of standard cells. Embodiments can also include generating a representation for the layout removing the existing output connections for each of the plurality of standard cells; and providing the representation of the layout to an autorouter. Also provided are embodiments for a system and computer program product for routing standard cells of an integrated circuit.
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Richard E Serton from Charlottesville, VA, age ~45 Get Report