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Regis J Nero

from Trafford, PA
Age ~67
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Related to:
Jack O Burns, 91Paul E Miller, 62Ashleigh D Nero, 39Patti C Nero, 66David J Nero, 43Calley L Nero, 42Mark W Nero, 66Paul S Nero, 60Barbara J Nero, 90
Connected to:
Alex M Nero, 41Alexandra J Nero, 29Angelo G Nero, 32Anne M Nero, 60Annie Nero, 41Bethany J Nero, 113Carol A Nero, 59David J Nero, 68Donna M Nero, 70Erin A Nero, 45

Regis Nero Phones & Addresses

  • 636 Penn Dr, Trafford, PA 15085
  • Murrysville, PA
  • 450 Folino Rd, Central City, PA 15926 (814) 754-4705
  • 3303 Carriage Cir, Export, PA 15632 (724) 733-3564
  • Delmont, PA

Work

Company: Independent contractor, medical device r&d Position: Electrical design engineer,

Education

School / High School: Carnegie Mellon University- Pittsburgh, PA 1986 Specialities: Computer Engineering

Skills

DESIGN EXPERIENCE Mixed Signal Archit... • Mixers • Filters) Miniature Antenna RFID (HF • UHF) EM Modeling (WIPL SW) Magnet... • Power) MOSFET Power Devices PCB Design &... • MSP430 • Si4010 Compliance (FCC • FDA • UL) Firmware (C • Assembly) FPGA (Verilog • VHDL) Bluetooth Low Energy EMI/EMC Compl... • Pspice)

Resumes

Resumes

Regis Nero Photo 1

Regis Nero Pittsburgh, PA

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Work:
Independent contractor, Medical Device R&D

Electrical Design Engineer,
Clearcount Medical Solutions
Pittsburgh, PA
2009 to 2012
Staff Engineer, Medical Device R&D
Tollgrade Communications
Cheswick, PA
1996 to 2009
System Architect/Manager, Smart Grid Product Development
Westinghouse Electric Corporation

1992 to 1996
Senior Design Engineer
Westinghouse Electric Corporation
Monroeville, PA
1982 to 1996
Westinghouse Electric Corporation

1988 to 1992
Senior Design Engineer
Westinghouse Electric Corporation

1985 to 1988
Design Engineer
Westinghouse Electric Corporation

1982 to 1985
Design Engineer
Education:
Carnegie Mellon University
Pittsburgh, PA
1986 to 1988
Computer Engineering
Rochester Institute of Technology
Rochester, NY
1982
Bachelor in Electrical Engineering Technology
Skills:
DESIGN EXPERIENCE Mixed Signal Architectures Low Level Analog Processing RF (LNA, Mixers, Filters) Miniature Antenna RFID (HF, UHF) EM Modeling (WIPL SW) Magnetics (Ferrite, Power) MOSFET Power Devices PCB Design & Layout Miniature Wireless PICs, MSP430, Si4010 Compliance (FCC, FDA, UL) Firmware (C, Assembly) FPGA (Verilog, VHDL) Bluetooth Low Energy EMI/EMC Compliance Orcad (Schematic, Pspice)

Publications

Us Patents

Apparatus And Method For Measuring Loop Insertion Loss Single-Endedly

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US Patent:
20060159231, Jul 20, 2006
Filed:
Jan 18, 2006
Appl. No.:
11/334239
Inventors:
Timothy Vitanza - Mars PA, US
Rebecca Ross - Apollo PA, US
Regis Nero - Export PA, US
Assignee:
Tollgrade Communications, Inc. - Wilmington DE
International Classification:
H04M 1/24
H04M 3/08
US Classification:
379001010, 379022000
Abstract:
The system and method of determining insertion loss of a telephone line under test (LUT) determines a first insertion loss as a function of plurality of different equivalent circuit values of the LUT determined at a plurality of different frequencies of a first set of discrete frequencies. A running standard deviation (rSTD) of a predicted length d of the LUT at each frequency of a second set of discrete frequencies is determined from the predicted lengths d of the LUT at and below said frequency. A second insertion loss is determined based on the pair of adjacent discrete frequencies of the second set of discrete frequencies that have the largest difference between their rSTDs. Based on a comparison of the first and second insertion losses to an expected insertion loss, one of these insertion losses is deemed to be the actual insertion loss of the LUT.

Apparatus And Method For Measuring Loop Insertion Loss Single-Endedly

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US Patent:
20070263776, Nov 15, 2007
Filed:
May 23, 2007
Appl. No.:
11/752664
Inventors:
Timothy Vitanza - Mars PA, US
Rebecca Ross - Apollo PA, US
Regis Nero - Export PA, US
Assignee:
TOLLGRADE COMMUNICATIONS, INC. - Wilmington DE
International Classification:
H04M 1/24
H04M 3/08
H04M 3/22
US Classification:
379001010
Abstract:
The system and method of determining insertion loss of a telephone line under test (LUT) determines a first insertion loss as a function of plurality of different equivalent circuit values of the LUT determined at a plurality of different frequencies of a first set of discrete frequencies. A running standard deviation (rSTD) of a predicted length d of the LUT at each frequency of a second set of discrete frequencies is determined from the predicted lengths d of the LUT at and below said frequency. A second insertion loss is determined based on the pair of adjacent discrete frequencies of the second set of discrete frequencies that have the largest difference between their rSTDs. Based on a comparison of the first and second insertion losses to an expected insertion loss, one of these insertion losses is deemed to be the actual insertion loss of the LUT.

Apparatus And Method For Measuring Loop Insertion Loss Single-Endedly

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US Patent:
20070263777, Nov 15, 2007
Filed:
May 24, 2007
Appl. No.:
11/752963
Inventors:
Timothy Vitanza - Mars PA, US
Rebecca Ross - Apollo PA, US
Regis Nero - Export PA, US
Assignee:
TOLLGRADE COMMUNICATIONS, INC. - Wilmington DE
International Classification:
H04M 1/24
H04M 3/08
H04M 3/22
US Classification:
379001010
Abstract:
The system and method of determining insertion loss of a telephone line under test (LUT) determines a first insertion loss as a function of plurality of different equivalent circuit values of the LUT determined at a plurality of different frequencies of a first set of discrete frequencies. A running standard deviation (rSTD) of a predicted length d of the LUT at each frequency of a second set of discrete frequencies is determined from the predicted lengths d of the LUT at and below said frequency. A second insertion loss is determined based on the pair of adjacent discrete frequencies of the second set of discrete frequencies that have the largest difference between their rSTDs. Based on a comparison of the first and second insertion losses to an expected insertion loss, one of these insertion losses is deemed to be the actual insertion loss of the LUT.

Power Distribution Monitoring System And Method

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US Patent:
20090240449, Sep 24, 2009
Filed:
Dec 22, 2008
Appl. No.:
12/341300
Inventors:
Jeffrey A. Gibala - North Huntingdon PA, US
Regis J. Nero - Export PA, US
Steven P. Day - Zelienople PA, US
Matthew G. Cimbala - Saxonburg PA, US
Roger A. Smith - Gibsonia PA, US
Assignee:
TOLLGRADE COMMUNICATIONS, INC. - Wilmington DE
International Classification:
G01R 21/00
G06F 19/00
US Classification:
702 62
Abstract:
A power distribution monitoring system includes a number of power line mounted monitors. Each monitor can acquire data regarding the delivery of electrical power in the power line, wirelessly transmit and receive messages, and electromagnetically acquire and store operating electrical power from electrical current flowing in the power line. The system also includes an aggregator that can wirelessly transmit and receive messages and wirelessly output beacon messages. In response to beacon signals wirelessly output by the aggregator, each monitor co-acts with the aggregator to dynamically build a wireless communication network for the wireless communication of the data acquired by the monitor regarding the delivery of electrical power in the power line to the aggregator.

Telephony Test System With Adjustable Output Impedance

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US Patent:
62857444, Sep 4, 2001
Filed:
Dec 22, 1999
Appl. No.:
9/402693
Inventors:
Regis J. Nero - Export PA
Louis W. Hiener - Pittsburgh PA
Richard A. Bair - Brackenridge PA
Frederick J. Kiko - Carlsbad CA
Leo W. Manuel - San Diego CA
Lester Mintzer - Santa Ana CA
Assignee:
Tollgrade Communications, Inc. - Wilmington DE
International Classification:
H04M 124
US Classification:
379 27
Abstract:
A telephone test system (2) includes a controller (4), a programmable gate array (PGA) (24) and a digital signal processor (DSP) (26) connected by a common bus (20). The PGA (24) includes an output connected to an input of a digital-to-analog converter (DAC) (36) and input connected to an output of an analog-to-digital converter (ADC) (32). A driver circuit (46) is connected between the DAC (36) and a telephone circuit (60) and between the ADC (32) and the telephone circuit (60). Under the control of the DSP (26), the driver circuit (46) generates voltages to the telephone circuit (60) and samples the response of the telephone circuit (60) to such generated voltages. The driver circuit (46) includes control inputs for receiving from the PGA (24) an impedance adjust signal (D) and a resistance adjust signal (R). An output impedance (124) of the driver circuit (46) connected to the telephone circuit (60) is adjustable as a function of the impedance adjust signal (D) and/or the resistance adjust signal (R).
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Regis J Nero from Trafford, PA, age ~67 Get Report