Resumes
Resumes

Master Engineer Design Verification
View pageLocation:
Austin, TX
Industry:
Semiconductors
Work:
Broadcom
Master Engineer Design Verification
Lifesize Aug 2009 - Jun 2012
Senior Design Verification Engineer
Zocalo Tech Jan 2009 - Jul 2009
Manager of Customer Support
Rmi Corporation Oct 2007 - Nov 2008
Performance Modeling and Design Verification Engineer
Conexant Oct 2006 - Oct 2007
Asic Design Staff
Master Engineer Design Verification
Lifesize Aug 2009 - Jun 2012
Senior Design Verification Engineer
Zocalo Tech Jan 2009 - Jul 2009
Manager of Customer Support
Rmi Corporation Oct 2007 - Nov 2008
Performance Modeling and Design Verification Engineer
Conexant Oct 2006 - Oct 2007
Asic Design Staff
Education:
Florida State University 1991 - 1996
Bachelors, Bachelor of Science In Electrical Engineering, Electrical Engineering Winter Park High School 1987 - 1991
Bachelors, Bachelor of Science In Electrical Engineering, Electrical Engineering Winter Park High School 1987 - 1991
Skills:
Verilog
Soc
Asic
Systemverilog
Integrated Circuit Design
Fpga
Perl
Functional Verification
Semiconductors
Vmm
Debugging
Ic
Vera
C++
Application Specific Integrated Circuits
System on A Chip
C
Field Programmable Gate Arrays
Embedded Systems
Uvm
Soc
Asic
Systemverilog
Integrated Circuit Design
Fpga
Perl
Functional Verification
Semiconductors
Vmm
Debugging
Ic
Vera
C++
Application Specific Integrated Circuits
System on A Chip
C
Field Programmable Gate Arrays
Embedded Systems
Uvm