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Ray E Bloker

from Los Gatos, CA
Age ~66

Ray Bloker Phones & Addresses

  • 130 Highland Ave, Los Gatos, CA 95030 (408) 354-8815
  • 918 E West Dr, Murphys, CA 95247 (209) 728-0130
  • Manitou Springs, CO
  • 1555 Hervey Ln, San Jose, CA 95125 (408) 292-7345
  • Campbell, CA
  • Dallas, TX
  • Santa Clara, CA

Publications

Us Patents

Dynamic Node Keeper System And Method

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US Patent:
7221189, May 22, 2007
Filed:
Aug 8, 2005
Appl. No.:
11/199950
Inventors:
Ray Bloker - San Jose CA, US
Parag Gupta - San Jose CA, US
Assignee:
Transmeta Corporation - Santa Clara CA
International Classification:
H03K 19/096
US Classification:
326 98, 326121, 36518905
Abstract:
The present invention system and method provides voltage level support for an output target signal (e. g. , a dynamic node output signal) that “keeps” the output target signal at a particular voltage level with efficient suspension of the voltage level maintenance or support during an evaluation transition period (e. g. , a read operation) of the output target signal.

Dynamic Node Keeper System And Method

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US Patent:
6940314, Sep 6, 2005
Filed:
Dec 31, 2002
Appl. No.:
10/334264
Inventors:
Ray Bloker - San Jose CA, US
Parag Gupta - San Jose CA, US
Assignee:
Transmeta Corporation - Santa Clara CA
International Classification:
H03K019/096
US Classification:
326 98, 326121
Abstract:
The present invention system and method provides voltage level support for an output target signal (e. g. , a dynamic node output signal) that “keeps” the output target signal at a particular voltage level with efficient suspension of the voltage level maintenance or support during an evaluation transition period (e. g. , a read operation) of the output target signal.

Method And Circuit For Reducing Current Surge

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US Patent:
20160139656, May 19, 2016
Filed:
Jan 21, 2016
Appl. No.:
15/003752
Inventors:
- Irvine CA, US
Bruce KAUFFMANN - Santa Clara CA, US
Ray BLOKER - Los Gatos CA, US
International Classification:
G06F 1/32
Abstract:
Systems and methods are provided for reducing surge current in power gated designs. In one aspect, a storage capacitor supplies a portion of the current used to power up a circuit. The storage capacitor may be charged from a power supply or other source. When the circuit is to be powered up, the circuit is connected to the power supply and the storage capacitor. As a result, current is supplied to the circuit from the power supply and the storage capacitor to power up the circuit. Because a portion of the current used to power up the circuit is supplied from the storage capacitor, the amount of current needed from the power supply to power up the circuit can be reduced, thereby reducing current surge through the power supply. The storage capacitor may be shared by multiple circuits.

Method And Circuit For Reducing Current Surge

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US Patent:
20140097702, Apr 10, 2014
Filed:
Oct 4, 2012
Appl. No.:
13/645427
Inventors:
- Irvine CA, US
Bruce KAUFFMANN - Santa Clara CA, US
Ray BLOKER - Los Gatos CA, US
Assignee:
BROADCOM CORPORATION - Irvine CA
International Classification:
H01H 47/00
US Classification:
307115
Abstract:
Systems and methods are provided for reducing surge current in power gated designs. In one aspect, a storage capacitor supplies a portion of the current used to power up a circuit. The storage capacitor may be charged from a power supply or other source. When the circuit is to be powered up, the circuit is connected to the power supply and the storage capacitor. As a result, current is supplied to the circuit from the power supply and the storage capacitor to power up the circuit. Because a portion of the current used to power up the circuit is supplied from the storage capacitor, the amount of current needed from the power supply to power up the circuit can be reduced, thereby reducing current surge through the power supply. The storage capacitor may be shared by multiple circuits.
Ray E Bloker from Los Gatos, CA, age ~66 Get Report