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Raviprasad V Mummidi

from Mountain View, CA
Age ~46
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Also known as:
Raviprasad V Mummidi-Venkatesha, Raviprasad V Mummudi, Venkate Raviprasad Mummidi, Ravi Prdad Mummidi, Raviprasad E, D Mummidi
Related to:
Raviprasad V Mummudi
Connected to:
Dante G Mummolo, 77Felix Mummolo, 73Nicholas A Mumola, 82Allen D Mumper, 79Christy M Mumper, 71Karrianne S Mumper, 54Mark A Mumper, 58Sally J Mumper, 80Teresa R Mumper, 50Velma M Mumper, 101

Raviprasad Mummidi Phones & Addresses

  • Mountain View, CA
  • Santa Clara, CA

Skills

Virtualization • Linux • Vmware • Hypervisor • Operating Systems • Linux Kernel • X86 • System Architecture • C • Virtual Memory • Assembly Language • Android • Fault Tolerance • Arm • Amazon Ec2 • Windows • Hyper V • Device Drivers • Cloud Computing

Industries

Computer Software

Resumes

Resumes

Raviprasad Mummidi Photo 1

Raviprasad Mummidi

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Location:
San Francisco, CA
Industry:
Computer Software
Skills:
Virtualization
Linux
Vmware
Hypervisor
Operating Systems
Linux Kernel
X86
System Architecture
C
Virtual Memory
Assembly Language
Android
Fault Tolerance
Arm
Amazon Ec2
Windows
Hyper V
Device Drivers
Cloud Computing

Publications

Us Patents

System And Method To Reduce Trace Faults In Software Mmu Virtualization

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US Patent:
8359422, Jan 22, 2013
Filed:
Jun 26, 2009
Appl. No.:
12/492766
Inventors:
Qasim Ali - West Lafayette IN, US
Raviprasad Mummidi - Mountain View CA, US
Kiran Tati - Santa Clara CA, US
Assignee:
VMware, Inc. - Palo Alto CA
International Classification:
G06F 12/00
G06F 13/00
G06F 13/28
US Classification:
711 6, 711159, 711203, 718 1
Abstract:
A system for identifying an exiting process and removing traces and shadow page table pages corresponding to the process' page table pages. An accessed minimum virtual address is maintained corresponding to an address space. In one embodiment, whenever a page table entry corresponding to the accessed minimum virtual address changes from present to not present, the process is determined to be exiting and removal of corresponding trace and shadow page table pages is begun. In a second embodiment, consecutive present to not-present PTE transitions are tracked for guest page tables on a per address space basis. When at least two guest page tables each has at least four consecutive present to not-present PTE transitions, a next present to not-present PTE transition event in the address space leads to the corresponding guest page table trace being dropped and the shadow page table page being removed.

System And Method To Prioritize Large Memory Page Allocation In Virtualized Systems

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US Patent:
8364932, Jan 29, 2013
Filed:
Oct 29, 2010
Appl. No.:
12/915236
Inventors:
Qasim Ali - Santa Clara CA, US
Raviprasad Mummidi - Mountain View CA, US
Vivek Pandey - Bangalore, IN
Kiran Tati - Santa Clara CA, US
Assignee:
VMware, Inc. - Palo Alto CA
International Classification:
G06F 12/00
G06F 13/00
G06F 13/28
G06F 21/00
G06F 9/46
US Classification:
711206, 711 6, 711205, 718104
Abstract:
The prioritization of large memory page mapping is a function of the access bits in the L1 page table. In a first phase of operation, the number of set access bits in each of the L1 page tables is counted periodically and a current count value is calculated therefrom. During the first phase, no pages are mapped large even if identified as such. After the first phase, the current count value is used to prioritize among potential large memory pages to determine which pages to map large. The system continues to calculate the current count value even after the first phase ends. When using hardware assist, the access bits in the nested page tables are used and when using software MMU, the access bits in the shadow page tables are used for large page prioritization.

Hardware Interrupt Arbitration In Virtualized Computer Systems

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US Patent:
8612659, Dec 17, 2013
Filed:
Dec 14, 2010
Appl. No.:
12/967979
Inventors:
Benjamin C. Serebrin - Sunnyvale CA, US
Raviprasad Mummidi - Mountain View CA, US
Assignee:
VMware, Inc. - Palo Alto CA
International Classification:
G06F 13/24
US Classification:
710262, 710264, 718 1
Abstract:
Hardware interrupts are routed to one of multiple processors of a virtualized computer system based on priority values assigned to the codes being executed by the processors. Each processor dynamically updates a priority value associated with code being executed thereby, and when a hardware interrupt is generated, the hardware interrupt is routed to the processor that is executing a code with the lowest priority value to handle the hardware interrupt. As a result, routing of the interrupts can be biased away from processors that are executing high priority tasks or where context switch might be computationally expensive.

Method And System For Enabling Checkpointing Fault Tolerance Across Remote Virtual Machines

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US Patent:
20110289345, Nov 24, 2011
Filed:
May 18, 2010
Appl. No.:
12/781875
Inventors:
Ole Agesen - Menlo Park CA, US
Raviprasad Mummidi - Mountain View CA, US
Pratap Subrahmanyam - Saratoga CA, US
Assignee:
VMWARE, INC. - Palo Alto CA
International Classification:
G06F 11/20
G06F 12/16
G06F 11/16
G06F 11/00
US Classification:
714 411, 711162, 714E11084, 711E12103
Abstract:
A checkpointing fault tolerance network architecture enables a backup computer system to be remotely located from a primary computer system. An intermediary computer system is situated between the primary computer system and the backup computer system to manage the transmission of checkpoint information to the backup VM in an efficient manner. The intermediary computer system is networked to the primary VM through a high bandwidth connection but is networked to the backup VM through a lower bandwidth connection. The intermediary computer system identifies updated data corresponding to memory pages that have been least recently modified by the primary VM and transmits such updated data to the backup VM through the low bandwidth connection. In such manner, the intermediary computer system economizes the bandwidth capacity of the low bandwidth connection, holding back updated data corresponding to more recently modified memory pages, since such memory pages may be more likely to be updated again in the future.

Method And System For Enabling Checkpointing Fault Tolerance Across Remote Virtual Machines

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US Patent:
20120204061, Aug 9, 2012
Filed:
Apr 18, 2012
Appl. No.:
13/450249
Inventors:
Ole AGESEN - Menlo Park CA, US
Raviprasad MUMMIDI - Mountain View CA, US
Pratap SUBRAHMANYAM - Saratoga CA, US
Assignee:
VMware, Inc. - Palo Alto CA
International Classification:
G06F 12/16
G06F 17/30
G06F 11/14
US Classification:
714 15, 707649, 707E17005, 714E11118
Abstract:
A checkpointing fault tolerance network architecture enables a backup computer system to be remotely located from a primary computer system. An intermediary computer system is situated between the primary computer system and the backup computer system to manage the transmission of checkpoint information to the backup VM in an efficient manner. The intermediary computer system is networked to the primary VM through a first connection and is networked to the backup VM through a second connection. The intermediary computer system identifies updated data corresponding to memory pages that have been least recently modified by the primary VM and transmits such updated data to the backup VM through the first connection. In such manner, the intermediary computer system holds back updated data corresponding to more recently modified memory pages, since such memory pages may be more likely to be updated again in the future.

Method And System For Enabling Checkpointing Fault Tolerance Across Remote Virtual Machines

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US Patent:
20130067277, Mar 14, 2013
Filed:
Nov 6, 2012
Appl. No.:
13/670319
Inventors:
Raviprasad Mummidi - Mountain View CA, US
Assignee:
VMware, Inc. - Palo Alto CA
International Classification:
G06F 12/16
G06F 17/30
G06F 11/14
US Classification:
714 19, 707645, 707E17005, 714E11118
Abstract:
A checkpointing fault tolerance network architecture enables a backup computer system to be remotely located from a primary computer system. An intermediary computer system is situated between the primary computer system and the backup computer system to manage the transmission of checkpoint information to the backup VM in an efficient manner. The intermediary computer system is networked to the primary VM through a first connection and is networked to the backup VM through a second connection. The intermediary computer system identifies updated data corresponding to memory pages that have been less frequently modified by the primary VM and transmits such updated data to the backup VM through the first connection. In such manner, the intermediary computer system holds back updated data corresponding to more frequently modified memory pages, since such memory pages may be more likely to be updated again in the future.

Policy-Based Checkpointing Fault Tolerance Across Remote Virtual Machines

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US Patent:
20130097120, Apr 18, 2013
Filed:
Dec 12, 2012
Appl. No.:
13/712693
Inventors:
Raviprasad Mummidi - Mountain View CA, US
Assignee:
VMWARE, INC. - Palo Alto CA
International Classification:
G06F 17/30
US Classification:
707649
Abstract:
Embodiments include a checkpointing fault tolerance network architecture enables a first computer system to be remotely located from a second computer system. An intermediary computer system is situated between the first computer system and the second computer system to manage the transmission of checkpoint information from the first computer system to the second computer system in an efficient manner. The intermediary computer system responds to requests from the second computer system for updated data corresponding to memory pages selected by the second computer system, or memory pages identified through application of policy information defined by the second computer system.

System And Method To Reduce Trace Faults In Software Mmu Virtualization

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US Patent:
20130138864, May 30, 2013
Filed:
Jan 22, 2013
Appl. No.:
13/747159
Inventors:
Raviprasad MUMMIDI - Mountain View CA, US
Kiran TATI - Santa Clara CA, US
Assignee:
VMWARE, INC, - Palo Alto CA
International Classification:
G06F 12/08
US Classification:
711 6
Abstract:
A system for identifying an exiting process and removing traces and shadow page table pages corresponding to the process' page table pages. An accessed minimum virtual address is maintained corresponding to an address space. In one embodiment, whenever a page table entry corresponding to the accessed minimum virtual address changes from present to not present, the process is determined to be exiting and removal of corresponding trace and shadow page table pages is begun. In a second embodiment, consecutive present to not-present PTE transitions are tracked for guest page tables on a per address space basis. When at least two guest page tables each has at least four consecutive present to not-present PTE transitions, a next present to not-present PTE transition event in the address space leads to the corresponding guest page table trace being dropped and the shadow page table page being removed.
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Raviprasad V Mummidi from Mountain View, CA, age ~46 Get Report