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Ravi Kiran Nalla

from San Jose, CA
Age ~47
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Also known as:
Ravi K Nalla, Ravi Te Nalla
Phone and address:
7012 Livery Ln, San Jose, CA 95135
(408) 454-8587
Related to:
Chau T Nguyen, 38Thanh K Nguyen, 79Raul K NallaSmieha Nalla
Connected to:
Ganesh K Nalla, 48John B Nalla, 31Naresh Nalla, 40Phani Nalla, 36Rahul Nalla, 38Ramesh Nalla, 59Sundara C Nalla, 67Suresh Nalla, 50Venkata N Nalla, 50Tarun C Nallabelli, 41

Ravi Nalla Phones & Addresses

  • 7012 Livery Ln, San Jose, CA 95135 (408) 454-8587
  • Concord, NC
  • Chandler, AZ
  • 301 Perkins St, Oakland, CA 94610
  • El Cerrito, CA
  • Berkeley, CA
  • Sunnyvale, CA
  • Maricopa, AZ
  • Dawson, MN
  • 3472 Williams Rd, San Jose, CA 95117

Resumes

Resumes

Ravi Nalla Photo 1

Principal Hw Program Manager

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Location:
7012 Livery Ln, San Jose, CA 95135
Industry:
Computer Software
Work:
Lytro Inc. Aug 2012 - Oct 2013
Operations and Senior Manager, Manufacturing Technology
Microsoft Aug 2012 - Oct 2013
Principal Hw Program Manager
Lensvector Mar 2010 - Jul 2012
Principal Engineer
Intel Corporation 2005 - Feb 2010
Senior Packaging Engineer
Lawrence Berkeley National Laboratory 2004 - 2005
Postdoctoral Research Fellow
Education:
University of California, Berkeley 2001 - 2004
Doctorates, Doctor of Philosophy, Materials Science, Engineering University of California, Berkeley 1999 - 2001
Master of Science, Masters, Materials Science, Engineering Indian Institute of Technology, Madras 1995 - 1999
Bachelors, Bachelor of Technology, Metallurgical Engineering University of California
Skills:
Semiconductors
Manufacturing
R&D
Product Development
Failure Analysis
Design of Experiments
Engineering
Materials Science
Spc
Electronics Packaging
Testing
Thin Films
Program Management
Characterization
Process Simulation
Substrates
Design For Manufacturing
Engineering Management
Reliability
Silicon
Process Integration
Research and Development
Process Development
Optics
Optoelectronics
Supply Management
Electronic Packaging and Assembly
Supplier Management
New Product Introduction
Technology Development
Languages:
English
Ravi Nalla Photo 2

Ravi Nalla

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Publications

Us Patents

Method Of Enabling Solder Deposition On A Substrate And Electronic Package Formed Thereby

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US Patent:
7538429, May 26, 2009
Filed:
Aug 21, 2006
Appl. No.:
11/507697
Inventors:
Ravi Nalla - Chandler AZ, US
Charavana Gurumurthy - Higley AZ, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L 23/48
H01L 23/52
H01L 29/40
US Classification:
257737, 257738, 257739, 257780, 257781, 257E23021, 257E23069, 257E23162
Abstract:
An electronic package includes a substrate () and a solder resist layer () over the substrate. The solder resist layer has a plurality of solder resist openings () therein. The electronic package further includes a finish layer () in the solder resist openings, an electrically conducting layer () in the solder resist openings over the finish layer, and a solder material () in the solder resist openings over the electrically conducting layer. The electrically conducting layer electrically connects the solder resist openings in order to enable the electrokinetic deposition of the solder material.

Substrates For Optical Die Structures

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US Patent:
7583871, Sep 1, 2009
Filed:
Mar 20, 2008
Appl. No.:
12/052637
Inventors:
Omar J. Bchir - Phoenix AZ, US
Islam Salama - Chandler AZ, US
Charan Gurumurthy - Higley AZ, US
Houssam Jomaa - Phoenix AZ, US
Ravi Nalla - Chandler AZ, US
Yonggang Li - Chandler AZ, US
International Classification:
G02B 6/12
H01L 21/00
US Classification:
385 14, 385 49, 385 88, 385 89, 385 92, 438 26, 438 27, 438 29, 438 31
Abstract:
Package substrates for optical die structures are generally described. In one example, an apparatus includes a package substrate having one or more plated through hole (PTH) structures, an optical waveguide coupled with the package substrate, the optical waveguide having one or more input/output (I/O) optical signal pathways to route I/O signals to and from the package substrate, and one or more optical fibers coupled with the optical waveguide, the one or more optical fibers being disposed in the PTH structures to route I/O signals to and from a motherboard.

Microball Attachment Using Self-Assembly For Substrate Bumping

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US Patent:
7651021, Jan 26, 2010
Filed:
Dec 28, 2007
Appl. No.:
11/966943
Inventors:
Lakshmi Supriya - Chandler AZ, US
Ravi Nalla - Chandler AZ, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
B23K 31/02
US Classification:
22818022, 228246, 2282481
Abstract:
Electronic devices and methods for fabricating electronic devices are described. One method includes providing a substrate with a plurality of bonding pads thereon, and providing a plurality of solder microballs, the microballs including a coating thereon. The method also includes flowing the solder microballs onto the substrate and positioning the solder microballs on the bonding pads. The method also includes heating the solder microballs to reflow and form a joint between the solder microballs and the bonding pads. Other embodiments are described and claimed.

Barrier Layer For Fine-Pitch Mask-Based Substrate Bumping

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US Patent:
7776734, Aug 17, 2010
Filed:
May 26, 2006
Appl. No.:
11/441841
Inventors:
Ravi K. Nalla - Chandler AZ, US
Christine H. Tsau - Chandler AZ, US
Mark S. Hlad - Gainsville FL, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L 21/44
US Classification:
438612, 438106, 438613, 257E21508
Abstract:
A structure that may be used in substrate solder bumping comprises a substrate (), a solder resist layer () disposed over the substrate, a plurality of solder resist openings () in a surface () of the solder resist layer, a conformal barrier layer () having a first portion () over the surface of the solder resist layer and a second portion () in the solder resist openings, a mask layer () over the first portion of the conformal barrier layer, and a solder material () in the solder resist openings over the metal layer. The conformal barrier layer acts as a barrier against interaction between the solder resist layer and the mask layer during solder reflow.

Method Of Enabling Solder Deposition On A Substrate And Electronic Package Formed Thereby

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US Patent:
7825022, Nov 2, 2010
Filed:
Apr 30, 2009
Appl. No.:
12/387417
Inventors:
Ravi Nalla - Chandler AZ, US
Charavana Gurumurthy - Higley AZ, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L 21/44
US Classification:
438612, 438613, 438618, 438623, 438637, 438642, 257E23021
Abstract:
An electronic package includes a substrate () and a solder resist layer () over the substrate. The solder resist layer has a plurality of solder resist openings () therein. The electronic package further includes a finish layer () in the solder resist openings, an electrically conducting layer () in the solder resist openings over the finish layer, and a solder material () in the solder resist openings over the electrically conducting layer. The electrically conducting layer electrically connects the solder resist openings in order to enable the electrokinetic deposition of the solder material.

Optical Die Structures And Associated Package Substrates

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US Patent:
7831115, Nov 9, 2010
Filed:
Mar 20, 2008
Appl. No.:
12/052650
Inventors:
Omar Bchir - Phoenix AZ, US
Islam Salama - Chandler AZ, US
Charan Gurumurthy - Higley AZ, US
Houssam Jomaa - Phoenix AZ, US
Ravi Nalla - Chandler AZ, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G02B 6/12
G02B 6/036
US Classification:
385 14, 385 31, 385127
Abstract:
Optical die structures and associated package substrates are generally described. In one example, an electronic device includes a package substrate having a package substrate core, a dielectric layer coupled with the package substrate core, and one or more input/output (I/O) optical fibers coupled with the package substrate core or coupled with the build-up dielectric layer, or combinations thereof, the one or more I/O optical fibers to guide I/O optical signals to and from the package substrate wherein the one or more I/O optical fibers allow both input and output optical signals to travel through the one or more I/O optical fibers.

Method Of Forming Collapse Chip Connection Bumps On A Semiconductor Substrate

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US Patent:
7985622, Jul 26, 2011
Filed:
Aug 20, 2008
Appl. No.:
12/195339
Inventors:
Ravi Nalla - Chandler AZ, US
Islam Salama - Chandler AZ, US
Charan Gurumurthy - Higley AZ, US
Hamid Azimi - Chandler AZ, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L 21/44
B23K 31/00
US Classification:
438110, 2281791
Abstract:
A method of forming collapse chip connection bumps on a semiconductor substrate is provided. The method includes providing a semiconductor substrate having a plurality of bump vias on a top surface of the semiconductor substrate and electroplating the plurality of bump vias to form a plurality of via pads on the top surface of the semiconductor substrate. The method also includes disposing a plurality of solder microballs on the top surface of the semiconductor substrate, wherein each solder microball is placed on a corresponding via pad on the semiconductor substrate and reflowing the plurality of solder microballs to form the collapse chip connection bumps on the semiconductor substrate.

Barrier Layer For Fine-Pitch Mask-Based Substrate Bumping

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US Patent:
8183692, May 22, 2012
Filed:
Jul 14, 2010
Appl. No.:
12/835940
Inventors:
Ravi K. Nalla - Chandler AZ, US
Christine H. Tsau - Chandler AZ, US
Mark S. Hlad - Chandler AZ, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L 21/44
US Classification:
257738, 257737, 257E21508
Abstract:
A structure that may be used in substrate solder bumping comprises a substrate (), a solder resist layer () disposed over the substrate, a plurality of solder resist openings () in a surface () of the solder resist layer, a conformal barrier layer () having a first portion () over the surface of the solder resist layer and a second portion () in the solder resist openings, a mask layer () over the first portion of the conformal barrier layer, and a solder material () in the solder resist openings over the metal layer. The conformal barrier layer acts as a barrier against interaction between the solder resist layer and the mask layer during solder reflow.
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Ravi Kiran Nalla from San Jose, CA, age ~47 Get Report