Ravi K Bonam

20230116390, Apr 13, 2023

Oct 8, 2021

17/450325

- Armonk NY, US
Gauri KARVE - Cohoes NY, US
Effendi LEOBANDUNG - Stormville NY, US
Gangadhara Raja MUTHINTI - Albany NY, US
Ravi K. BONAM - Albany NY, US

G06F 30/398
G06F 21/44

The embodiments herein describe authenticating a photomask used to fabricate an IC or a wafer. Because the IC may have been fabricated at a third-party IC manufacturer, the customer may want to ensure the manufacturer did not mistakenly use an incorrect mask, or that the mask was not altered or replaced with a rogue mask by a nefarious actor. That is, the embodiments herein can be used to identify when an IC manufacture (whether trusted or not) mistakenly used the wrong photomask, or to verify that a third-party IC manufacturer did not tamper with or replace the authentic photomask with a rogue mask. Advantageously, the embodiments herein can create a secure IC fabrication process to catch mistakes as well as ensure that non-trusted third-parties did not introduce defects into the IC.

20210118854, Apr 22, 2021

Dec 28, 2020

17/135474

- Armonk NY, US
Fee Li Lie - Albany NY, US
Kevin Winstel - East Greenbush NY, US
Ravi K. Bonam - Albany NY, US
Iqbal Rashid Saraf - Glenmont NY, US
Dario Goldfarb - Dobbs Ferry NY, US
Daniel Corliss - Waterford NY, US
Dinesh Gupta - Hopewell Junction NY, US

H01L 25/065
H01L 23/48
H01L 29/16
H01L 23/46
H01L 23/538
H01L 23/00
H01L 23/522

The subject disclosure relates to 3D microelectronic chip packages with embedded coolant channels. The disclosed 3D microelectronic chip packages provide a complete and practical mechanism for introducing cooling channels within the 3D chip stack while maintaining the electrical connection through the chip stack. According to an embodiment, a microelectronic package is provided that comprises a first silicon chip comprising first coolant channels interspersed between first thru-silicon-vias (TSVs). The microelectronic chip package further comprises a silicon cap attached to a first surface of the first silicon chip, the silicon cap comprising second TSVs that connect to the first TSVs. A second silicon chip comprising second coolant channels can further be attached to the silicon cap via interconnects formed between a first surface of the second silicon chip and the silicon cap, wherein the interconnects connect to the second TSVs.

20210020529, Jan 21, 2021

Jul 20, 2019

16/517568

- Armonk NY, US
Kamal K. Sikka - Poughkeepsie NY, US
Joshua M. Rubin - Albany NY, US
Ravi K. Bonam - Albany NY, US
Ramachandra Divakaruni - Ossining NY, US
William J. Starke - Round Rock TX, US
Maryse Courmoyer - Granby, CA

H01L 23/13
H01L 23/538
H01L 23/532
H01L 27/24

The present invention includes a bridge connector with one or more semiconductor layers in a bridge connector shape. The shape has one or more edges, one or more bridge connector contacts on a surface of the shape, and one or more bridge connectors. The bridge connectors run through one or more of the semiconductor layers and connect two or more of the bridge connector contacts. The bridge connector contacts are with a tolerance distance from one of the edges. In some embodiments the bridge connector is a central bridge connector that connects two or more chips disposed on the substrate of a multi-chip module (MCM). The chips have chip contacts that are on an interior corner of the chip. The interior corners face one another. The central bridge connector overlaps the interior corners so that each of one or more of the bridge contacts is in electrical contact with each of one or more of the chip contacts. In some embodiments, overlap is minimized to permit more access to the surface of the chips. Arrays of MCMs and methods of making bridge connects are disclosed. Bridge connector shapes include: rectangular, window pane, plus-shaped, circular shaped, and polygonal-shaped.

20200294968, Sep 17, 2020

Mar 13, 2019

16/351757

- Armonk NY, US
Fee Li Lie - Albany NY, US
Kevin Winstel - East Greenbush NY, US
Ravi K. Bonam - Albany NY, US
Iqbal Rashid Saraf - Cobleskill NY, US
Dario Goldfarb - Dobbs Ferry NY, US
Daniel Corliss - Waterford NY, US
Dinesh Gupta - Hopewell Junction NY, US

H01L 25/065
H01L 23/48
H01L 29/16
H01L 23/46
H01L 23/538
H01L 23/00
H01L 23/522

The subject disclosure relates to 3D microelectronic chip packages with embedded coolant channels. The disclosed 3D microelectronic chip packages provide a complete and practical mechanism for introducing cooling channels within the 3D chip stack while maintaining the electrical connection through the chip stack. According to an embodiment, a microelectronic package is provided that comprises a first silicon chip comprising first coolant channels interspersed between first thru-silicon-vias (TSVs). The microelectronic chip package further comprises a silicon cap attached to a first surface of the first silicon chip, the silicon cap comprising second TSVs that connect to the first TSVs. A second silicon chip comprising second coolant channels can further be attached to the silicon cap via interconnects formed between a first surface of the second silicon chip and the silicon cap, wherein the interconnects connect to the second TSVs.

20180166277, Jun 14, 2018

Nov 29, 2017

15/825250

- Armonk NY, US
Ravi K. Bonam - Albany NY, US
Anuja Desilva - Slingerlands NY, US
Scott Halle - Slingerlands NY, US

H01L 21/033
H01L 21/02

A method is disclosed to prepare a substrate for photolithography. The method includes forming an underlayer over a surface of the substrate; depositing an interface hardmask layer on the underlayer using one of a vapor phase deposition process or an atomic layer deposition process; and forming a layer of extreme UV (EUV) resist on the interface hardmask layer, where the interface hardmask layer is comprised of material having a composition and properties tuned to achieve a certain secondary electron yield from the interface hardmask layer. Also disclosed is a structure configured for photolithography. The structure includes a substrate; an underlayer over a surface of the substrate; an interface hardmask layer disposed on the underlayer; and a layer of EUV resist disposed on the interface hardmask layer. The interface hardmask layer contains material having a composition and properties tuned to achieve a certain secondary electron yield from the interface hardmask layer.

20180166278, Jun 14, 2018

Nov 29, 2017

15/825301

- Armonk NY, US
Ravi K. Bonam - Albany NY, US
Anuja Desilva - Slingerlands NY, US
Scott Halle - Slingerlands NY, US

H01L 21/033
H01L 21/02

A method is disclosed to prepare a substrate for photolithography. The method includes forming an underlayer over a surface of the substrate; depositing an interface hardmask layer on the underlayer using one of a vapor phase deposition process or an atomic layer deposition process; and forming a layer of extreme UV (EUV) resist on the interface hardmask layer, where the interface hardmask layer is comprised of material having a composition and properties tuned to achieve a certain secondary electron yield from the interface hardmask layer. Also disclosed is a structure configured for photolithography. The structure includes a substrate; an underlayer over a surface of the substrate; an interface hardmask layer disposed on the underlayer; and a layer of EUV resist disposed on the interface hardmask layer. The interface hardmask layer contains material having a composition and properties tuned to achieve a certain secondary electron yield from the interface hardmask layer.

20160181050, Jun 23, 2016

Dec 21, 2015

14/976083

- Armonk NY, US
Ravi K. Bonam - Albany NY, US

H01J 1/34
H01J 9/12

A scalable, integrated multi-level photoemitter device of tapered design and method of manufacture using conventional CMOS manufacturing techniques. The photoemitter device has a tapered multi-level structure formed in a material layer of a substrate, each level comprising a layer of photoemissive material and a connecting portion, said connecting portion for connecting to an adjacent photoemissive material layer of a next successive level. A first photoemissive material layer of a first level is of a configuration having a first length or width dimension; and each successive layer includes a photoemissive material layer of successively smaller length or width dimensions

20150255241, Sep 10, 2015

Mar 10, 2014

14/202646

- Armonk NY, US
Ravi K. Bonam - Albany NY, US

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY

H01J 37/073
H01J 9/12
H01J 37/317
H01J 1/34

A scalable, integrated photoemitter device and method of manufacture using conventional CMOS manufacturing techniques. The photoemitter device has a first semiconductor substrate having a plurality of photonic sources formed on top in a first material layer, the plurality of photonic sources and the material layer forming a planar surface. A second substrate is bonded to the planar surface, the second substrate having a plurality of photoemitter structures formed on top in a second material layer, each photoemitter structure in alignment with a respective photonic source of the first substrate and configured to generate particle beams responsive to light from a respective light source. Additionally provided is a multi-level photoemitter of tapered design for implementation in the scalable, integrated photoemitter device. Conventional CMOS manufacturing techniques are also implemented to build the multi-level photoemitter of tapered design.