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Raphael Manalo Phones & Addresses

  • San Jose, CA

Work

Company: Sunpower corporation Jan 1, 2004 Position: Senior staff equipment development engineer

Education

School / High School: Batangas State University 2016 to 2016

Skills

Design of Experiments • Spc • Photovoltaics • Manufacturing • Solar Energy • Solar Cells • Failure Analysis • Cvd • Solidworks • Autocad • Semiconductors • Lpcvd • Fmea • Jmp • Characterization • Thin Films • Pecvd • Thermal Processing • Pcb Design • Silicon • Statistical Process Control • Solar Cell/Module Performance Characteri... • Solar Cell Manufacturing • Lamination • Jmp • Laminating • Inkjet Printing • Solar Module Manufacturing • Induction Soldering • Phase Gate Technology Development and De... • Programmable Logic Controller

Ranks

Certificate: Licensed Electronics and Communications Engineer

Industries

Renewables & Environment

Resumes

Resumes

Raphael Manalo Photo 1

Senior Staff Equipment Development Engineer

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Location:
San Francisco, CA
Industry:
Renewables & Environment
Work:
Sunpower Corporation
Senior Staff Equipment Development Engineer

Photocircuits Corporation Sep 2002 - Jan 2004
Product Support Technician

Nsg America Mar 2001 - Mar 2002
Research and Development Engineer
Education:
Batangas State University 2016 - 2016
Batangas State University 1995 - 2000
Skills:
Design of Experiments
Spc
Photovoltaics
Manufacturing
Solar Energy
Solar Cells
Failure Analysis
Cvd
Solidworks
Autocad
Semiconductors
Lpcvd
Fmea
Jmp
Characterization
Thin Films
Pecvd
Thermal Processing
Pcb Design
Silicon
Statistical Process Control
Solar Cell/Module Performance Characterization
Solar Cell Manufacturing
Lamination
Jmp
Laminating
Inkjet Printing
Solar Module Manufacturing
Induction Soldering
Phase Gate Technology Development and Deployment
Programmable Logic Controller
Certifications:
Licensed Electronics and Communications Engineer
License 21746

Publications

Us Patents

Dual Wafer Plating Fixture For A Continuous Plating Line

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US Patent:
20190301047, Oct 3, 2019
Filed:
Mar 7, 2019
Appl. No.:
16/295995
Inventors:
- San Jose CA, US
Paul W. Loscutoff - Castro Valley CA, US
Raphael M. Manalo - San Jose CA, US
Amold V. Castillo - Batangas, PH
Mohamad Ridzwan Mustafa - Johor Bahru, MY
Mark A. Kleshock - Phoenix AZ, US
Neil G. Bergstrom - Los Altos CA, US
International Classification:
C25D 17/08
C25D 7/12
C25D 17/00
Abstract:
A wafer plating fixture for use in simultaneously electroplating a two substrates. The wafer plating fixture including: an electrically conductive carrier bus; a plurality of contact clips electrically coupled to the carrier bus and configured to hold the two substrates in place and electrically couple the two substrates to the carrier bus; and a non-conductive substrate backer to separate the two substrates coupled to the carrier bus. A method of electroplating a plurality of substrates. The method including: mounting two substrates to be plated onto a wafer plating fixture; mounting the wafer plating fixture on a continuous belt of plating system; dipping the wafer plating fixture with the two substrates held thereon into an electroplating bath; and applying a voltage to the two substrates via the wafer plating fixture.
Raphael M Manalo from San Jose, CA, age ~46 Get Report