Resumes
Resumes
Ramkumar Prakasam Phones & Addresses
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Irvine, CA
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4604 Winding Way, San Jose, CA 95129 (408) 269-4490
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3517 Irlanda Way, San Jose, CA 95124 (408) 269-4490
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2650 Keystone Ave, Santa Clara, CA 95051 (408) 260-8026
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444 Saratoga Ave, Santa Clara, CA 95050 (408) 260-8026
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Milpitas, CA
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College Park, MD
Publications
Us Patents
Closed Loop Sub-Carrier Synchronization System
View pageUS Patent:
7529330, May 5, 2009
Filed:
May 9, 2008
Appl. No.:
12/118124
Inventors:
Alexander G. MacInnis - Ann Arbor MI, US
Aleksandr Movshovich - Santa Clara CA, US
Brad Delanghe - Sunnyvale CA, US
Ramkumar Prakasam - San Jose CA, US
Aleksandr Movshovich - Santa Clara CA, US
Brad Delanghe - Sunnyvale CA, US
Ramkumar Prakasam - San Jose CA, US
Assignee:
Broadcom Corporation - Irvine CA
International Classification:
H04L 7/00
US Classification:
375371
Abstract:
A system and method for synchronizing sub-carriers in a signal processing system. Various aspects of the present invention may comprise method steps and structure that receive a sampled signal. Various aspects may produce a synchronization signal based on the sampled signal. Various aspects may generate and store a cropped version of the received sampled signal. Various aspects may read a cropped sampled signal from memory that corresponds to the received sampled signal. Various aspects may generate a restored sampled signal by adding samples to the cropped sampled signal read from memory. Various aspects may, based on the synchronization signal, output the restored sampled signal coarsely synchronized to the received sampled signal. Various aspects may determine a phase difference between the output restored sampled signal and the output received sub-carrier. Various aspects may adjust the phase of the restored sampled signal in response to the determined phase difference.
Context Adaptive Binary Arithmetic Code Decoding Engine
View pageUS Patent:
7630440, Dec 8, 2009
Filed:
Jul 23, 2004
Appl. No.:
10/897546
Inventors:
Ramkumar Prakasam - Santa Clara CA, US
International Classification:
H04N 7/12
G06K 9/46
G06K 9/46
US Classification:
37524025, 382247
Abstract:
Methods and systems for selecting contexts during decoding of arithmetic code are disclosed. Aspects of the method may comprise assigning a plurality of default context identifiers to a plurality of current syntax elements within a current macroblock. A plurality of adjacent context identifiers may be acquired, where the adjacent context identifiers may be associated with a plurality of syntax elements within at least one macroblock adjacent to the current macroblock. At least one of the plurality of adjacent context identifiers may be selected utilizing at least one of the default context identifiers. Each of the default context identifiers may comprises a binary value. A top-adjacent context identifier associated with a syntax element within a top-adjacent macroblock to the current macroblock may be acquired. A left-adjacent context identifier associated with a syntax element within a left-adjacent macroblock to the current macroblock may be acquired.
Context Adaptive Binary Arithmetic Code Decoding Engine
View pageUS Patent:
7769088, Aug 3, 2010
Filed:
May 26, 2004
Appl. No.:
10/854592
Inventors:
Ramkumar Prakasam - Santa Clara CA, US
Alexander G MacInnis - Los Altos CA, US
Olive Tao - Saratoga CA, US
Xiaodong Xie - Fremont CA, US
Alexander G MacInnis - Los Altos CA, US
Olive Tao - Saratoga CA, US
Xiaodong Xie - Fremont CA, US
Assignee:
Broadcom Corporation - Irvine CA
International Classification:
H04N 7/12
G06K 9/46
G06K 9/46
US Classification:
37524025, 382247
Abstract:
A CABAC decoding engine is devised to cover all aspects of decoding all CABAC-coded syntax elements for AVC. This CABAC decoding engine acts like a Co-processor to another Processor (CPU), which guides the decoding of the bit stream. The CABAC decoding engine or Co-processor has the following highlights: unique context model retrieving and storing method is developed to allow a complete syntax element to be decoded in one hardware (H/W) execution cycle (not necessarily one clock cycle. ); H/W assisted approach is provided to accelerate context model initialization; H/W based approach is incorporated to allow fast de-binarization; H/W based approach is provided to allow a block of syntax elements to be decoded instead of one by one; and dedicated H/W accelerators are incorporated to decode special syntax elements.
Closed Loop Sub-Carrier Synchronization System
View pageUS Patent:
7372929, May 13, 2008
Filed:
Mar 5, 2004
Appl. No.:
10/794601
Inventors:
Alexander G. MacInnis - Ann Arbor MI, US
Aleksandr Movshovich - Santa Clara CA, US
Brad Delanghe - Sunnyvale CA, US
Ramkumar Prakasam - San Jose CA, US
Aleksandr Movshovich - Santa Clara CA, US
Brad Delanghe - Sunnyvale CA, US
Ramkumar Prakasam - San Jose CA, US
Assignee:
Broadcom Corporation - Irvine CA
International Classification:
H04L 7/00
US Classification:
375354, 348549
Abstract:
A system and method for synchronizing sub-carriers in a signal processing system. Various aspects of the present invention may comprise method steps and structure that receive a sampled signal. Various aspects may produce a synchronization signal based on the sampled signal. Various aspects may generate and store a cropped version of the received sampled signal. Various aspects may read a cropped sampled signal from memory that corresponds to the received sampled signal. Various aspects may generate a restored sampled signal by adding samples to the cropped sampled signal read from memory. Various aspects may, based on the synchronization signal, output the restored sampled signal coarsely synchronized to the received sampled signal. Various aspects may determine a phase difference between the output restored sampled signal and the output received sub-carrier. Various aspects may adjust the phase of the restored sampled signal in response to the determined phase difference.
Closed Loop Sub-Carrier Synchronization System
View pageUS Patent:
8130885, Mar 6, 2012
Filed:
Apr 30, 2009
Appl. No.:
12/433396
Inventors:
Alexander G. MacInnis - Ann Arbor MI, US
Aleksandr Movshovich - Santa Clara CA, US
Brad Delanghe - Sunnyvale CA, US
Ramkumar Prakasam - San Jose CA, US
Aleksandr Movshovich - Santa Clara CA, US
Brad Delanghe - Sunnyvale CA, US
Ramkumar Prakasam - San Jose CA, US
Assignee:
Broadcom Corporation - Irvine CA
International Classification:
H04L 7/00
US Classification:
375354
Abstract:
A system and method for synchronizing sub-carriers in a signal processing system. Various aspects of the present invention may comprise method steps and structure that receive a sampled signal. Various aspects may produce a synchronization signal based on the sampled signal. Various aspects may generate and store a cropped version of the received sampled signal. Various aspects may read a cropped sampled signal from memory that corresponds to the received sampled signal. Various aspects may generate a restored sampled signal by adding samples to the cropped sampled signal read from memory. Various aspects may, based on the synchronization signal, output the restored sampled signal coarsely synchronized to the received sampled signal. Various aspects may determine a phase difference between the output restored sampled signal and the output received sub-carrier. Various aspects may adjust the phase of the restored sampled signal in response to the determined phase difference.
Motion Vector Reconstruction In An Entropy Decoder
View pageUS Patent:
20050281336, Dec 22, 2005
Filed:
Jun 16, 2005
Appl. No.:
11/154325
Inventors:
Alexander Maclnnis - Lake Oswego OR, US
Ramkumar Prakasam - Santa Clara CA, US
Sheng Zhong - San Jose CA, US
Ramkumar Prakasam - Santa Clara CA, US
Sheng Zhong - San Jose CA, US
International Classification:
H04B001/66
H04N011/02
H04N011/04
H04N007/12
H04N011/02
H04N011/04
H04N007/12
US Classification:
375240160, 375240230, 375240030, 375240180, 375240250
Abstract:
Presented herein are system(s), method(s), and apparatus for motion vector reconstruction in an entropy decoder. In one embodiment of the present invention, there is presented a method for decoding a bitstream. The method comprises reconstructing at least one motion vector from the bitstream at a first stage in a pipeline; and entropy decoding the bitstream with the at least one reconstructed motion vector at the first stage.
Data And Phase Locking Buffer Design In A Two-Way Handshake System
View pageUS Patent:
20060268992, Nov 30, 2006
Filed:
May 31, 2005
Appl. No.:
11/140833
Inventors:
Genkun Yang - Sarasota CA, US
Ramkumar Prakasam - Santa Clara CA, US
Ramkumar Prakasam - Santa Clara CA, US
International Classification:
H04N 11/04
US Classification:
375240240, 713400000
Abstract:
A data and phase locking buffer design in a two-way handshake system is provided and may comprise sequentially locking pipelining of data in a synchronized pipeline and draining the synchronized pipeline of the data. The data may be synchronously accepted at a substantially similar time by contiguous pipeline stages that have data to be accepted. A ready signal, which may be processed after being generated by a present pipeline stage of the synchronized pipeline, may be communicated to a subsequent pipeline stage of the synchronized pipeline. An accept signal may be communicated from a present pipeline stage to a previous pipeline stage. A drain signal may be generated for draining the data from the synchronized pipeline. The drain signal may be asserted and deasserted based on end of line information in the data.