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Rajiv M Ranade

from Santa Rosa, CA
Age ~58
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Also known as:
Rajiv Vibhava Ranade, Rajiv V Ranade, Raj B
Related to:
Ashok Katdare, 74Vibhava R Ranade, 54Maya V Katdare, 77Sudha V Katdare
Connected to:
Aarti K Ranade, 44Madhuri P Ranade, 62Meghna A Ranade, 45Rajeev K Ranade, 37Shailesh S Ranade, 52Smita V Ranade, 46Sunil G Ranade, 56Uma S Ranade, 41Aditya G Ranadive, 33Amol S Ranadive, 54

Rajiv Ranade Phones & Addresses

  • Santa Rosa, CA
  • 18 Mill Towne Dr, Waterford, NY 12188 (518) 982-1811
  • Clifton Park, NY
  • 2 Noel Ct, Brewster, NY 10509 (845) 278-0935
  • 5 Loudon Dr, Fishkill, NY 12524 (845) 897-5391
  • Somerset, NJ
  • Fayetteville, AR
  • 18 Mill Towne Dr, Waterford, NY 12188 (860) 488-7380

Work

Position: Professional/Technical

Education

Degree: Graduate or professional degree

Publications

Us Patents

Elimination/Reduction Of Black Silicon In Dt Etch

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US Patent:
6489249, Dec 3, 2002
Filed:
Jun 20, 2000
Appl. No.:
09/597441
Inventors:
Gangadhara S. Mathad - Poughkeepsie NY
Rajiv Ranade - Brewster NY
Assignee:
Infineon Technologies AG - Munich
International Classification:
H01L 2100
US Classification:
438729, 1563453, 156915, 216 67, 438710
Abstract:
In a method of etching a wafer in a plasma etch reactor, the improvement of conducting etching to reduce or eliminate âblack siliconâ comprising: a) providing a plasma etch reactor comprising walls defining an etch chamber; b) providing a plasma source chamber remote from and in communication with the etch chamber to provide a plasma to the etch chamber, and a wafer chuck or pedestal disposed in the etch chamber to seat a wafer; c) providing a dielectric wall in proximity to and around a periphery of the wafer; d) providing a modification to a lower Rf electrode by interposing conductor means into an extension of Vdc flat sheath boundary relationship to the dielectric wall means and the wafer or in substitution for the dielectric wall; e) forming a plasma within the plasma source chamber and providing the plasma to the etch chamber; and f) supplying Rf energy to the wafer chuck to assist etching of the wafer by forming electric fields between the upper surface of the wafer and the walls of the etch chamber, to provide extension of a Vdc flat sheath boundary beyond and into a defocusing relationship to the wafer edge to reduce mask erosion and eliminate occurrence of âblack siliconâ formation.

Method Of Deep Trench Formation With Improved Profile Control And Surface Area

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US Patent:
6544838, Apr 8, 2003
Filed:
Mar 13, 2001
Appl. No.:
09/805071
Inventors:
Rajiv Ranade - Brewster NY
Munir D. Naeem - Poughkeepsie NY
Gangadhara S. Mathad - Poughkeepsie NY
Assignee:
Infineon Technologies AG - Munich
International Business Machines Corporation - Armonk NY
International Classification:
H01L 218242
US Classification:
438244, 438243, 438386, 438387
Abstract:
A method for etching trenches includes providing a patterned mask stack on a substrate. A trench is etched in the substrate by forming a tapered-shaped trench portion of the trench, which narrows with depth in the substrate by employing a first plasma chemistry mixture including O , HBr and NF. An extended portion of the trench is formed by etching a second profile deeper and wider than the tapered-shaped trench portion in the substrate by employing a second plasma chemistry mixture including O , HBr and SF or F.

Method Of Manufacturing Circuit With Buried Strap Including A Liner

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US Patent:
6605504, Aug 12, 2003
Filed:
Jun 28, 2002
Appl. No.:
10/186043
Inventors:
Venkatachalam C. JaiPrakash - Sunnyvale CA
Rajiv Ranade - Brewster NY
Assignee:
Infineon Technologies AG
International Classification:
H01L 218242
US Classification:
438243, 438244, 438248, 438386, 438387, 438391
Abstract:
Semiconductor devices having trenches with buried straps therein preventing lateral out-diffusion of dopant are provided along with methods of fabricating such semiconductor devices.

Method To Increase The Etch Rate And Depth In High Aspect Ratio Structure

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US Patent:
6709917, Mar 23, 2004
Filed:
May 13, 2002
Appl. No.:
10/145230
Inventors:
Siddhartha Panda - Beacon NY
Rajiv M. Ranade - Brewster NY
Gangadhara S. Mathad - Poughkeepsie NY
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 218242
US Classification:
438243, 438386, 438735
Abstract:
A method of fabricating a high aspect ratio deep trench in a semiconductor substrate comprising reducing the formation of a passivation film during the etching of the trench by including a first step of contacting the substrate in which the deep trench is to be formed with a fluorine poor or low concentration of a fluorine gas in the plasma of etchant gases for etching the high aspect ratio deep trench, followed by a second step of increasing the concentration of the fluorine containing gas to create a fluorine-rich plasma while lowering the chamber pressure of the reactor and RF power. Preferably, the second step is introduced periodically during the etching of a deep trench in an alternating manner.

Method Of Etching High Aspect Ratio Openings

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US Patent:
6743727, Jun 1, 2004
Filed:
Jun 5, 2001
Appl. No.:
09/874109
Inventors:
Gangadhara S. Mathad - Poughkeepsie NY
Siddhartha Panda - Beacon NY
Rajiv M. Ranade - Brewster NY
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 2100
US Classification:
438695, 438702, 438703, 438714, 216 37, 216 46, 216 67, 216 79
Abstract:
A method of etching a deep, high aspect ratio opening in a silicon substrate includes etching the substrate with a first plasma formed using a first gaseous mixture including a bromine containing gas, an oxygen containing gas and a first fluorine containing gas. The etching process with the first gaseous mixture produces a sidewall passivating deposit, which builds up near the opening entrance. To reduce this buildup, and to increase the average etching rate, the sidewall passivating deposit is periodically thinned by forming a second plasma using a mixture containing silane and a second fluorine containing gas. The substrate remains in the same plasma reactor chamber during the entire process and the plasma is continuously maintained during the thinning step. Holes of a depth greater than 40 times the width may be produced using repeated cycles of etching and thinning.

Method To Fill Deep Trench Structures With Void-Free Polysilicon Or Silicon

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US Patent:
6809005, Oct 26, 2004
Filed:
Mar 12, 2003
Appl. No.:
10/386880
Inventors:
Rajiv Ranade - Beacon NY
Gangadhara S. Mathad - Poughkeepsie NY
Kevin K. Chan - Staten Island NY
Subhash B. Kulkarni - Cortlandt Manor NY
Assignee:
Infineon Technologies AG
International Business Machines Corporation - Armonk NY
International Classification:
H01L 2176
US Classification:
438426, 438388, 438422
Abstract:
The present invention provides methods of producing trench structures having substantially void-free filler material therein. The fillers may be grown from a liner material such as polysilicon formed along the sidewalls of the trench. Previously formed voids may be healed by exposing the voids and growing epitaxial silicon.

Method To Achieve Increased Trench Depth, Independent Of Cd As Defined By Lithography

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US Patent:
6821864, Nov 23, 2004
Filed:
Mar 7, 2002
Appl. No.:
10/093789
Inventors:
Kevin K. Chan - Staten Island NY
Subhash B. Kulkarni - Cortlandt Manor NY
Gangadhara S. Mathad - Poughkeepsie NY
Rajiv M. Ranade - Brewster NY
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 2176
US Classification:
438429, 438269
Abstract:
A method of forming at least one deep trench structure having an increased trench depth is provided. The method includes providing at least one deep trench having sidewalls that extend to a common bottom wall in a surface of a substrate. Each deep trench has initial dimensions that are wider than targeted dimensions for the deep trenches. To reduce the initial dimensions to that of the targeted dimensions, an epitaxial silicon film is formed selectively or non-selectively on at least some portions of the sidewalls using a low-temperature ultra-high vacuum epitaxial silicon growth tehnique.

Method For Dry Etching Deep Trenches In A Substrate

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US Patent:
6821900, Nov 23, 2004
Filed:
Jan 9, 2001
Appl. No.:
09/757123
Inventors:
Satish Athavale - Fishkill NY
Rajiv Ranade - Brewster NY
Munir Naeem - Poughkeepsie NY
Gangadhara Swami Mathad - Poughkeepsie NY
Assignee:
Infineon Technologies AG - Munich
International Business Machines - Armonk NY
International Classification:
H01L 21311
US Classification:
438700, 438710, 438713, 438714, 438719
Abstract:
A method for etching trenches in a substrate secures a wafer to an electrode in a plasma chamber and heats the wafer to a temperature of greater than 200 degrees Celsius. The wafer is exposed to a reactive plasma to etch trenches into the substrate of the wafer with minimal redeposition of etch by-products to avoid pinching off the trench and to promote further etching.
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Rajiv M Ranade from Santa Rosa, CA, age ~58 Get Report