Rajesh B Khamankar from 715 Beal Ln, Coppell, TX 75019, Phone: (972) 393-5660

Resumes

Engagement Director

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Location:

Dallas, TX

Industry:

Semiconductors

Work:

Pdf Solutions
Engagement Director
Pdf Solutions Jan 2013 - Dec 2016
Principal Engineer
Texas Instruments Feb 2011 - Nov 2012
Manager, Process Integration, 28Nm High Performance Cmos and 90Nm Ultra Low Leakage Embedded Nvram
Texas Instruments 2008 - 2011
Manager, Process Integration, 40Nm High Performance Cmos
Texas Instruments 1995 - 2008
Senior Member of Technical Staff, Silicon Technology Development

Education:

The University of Texas at Austin 1991 - 1995
Doctorates, Doctor of Philosophy, Electrical Engineering

Skills:

Cmos
Silicon
Semiconductors
Ic
Embedded Systems
Semiconductor Industry
Mixed Signal
Analog
Soc
Yield
Integration
Engineering Management

Publications

Us Patents

Hexagonally Symmetric Integrated Circuit Cell

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US Patent:

6342420, Jan 29, 2002

Filed:

Apr 3, 2000

Appl. No.:

09/542002

Inventors:

Akitoshi Nishimura - Tsuchiura, JP
Yasutoshi Okuno - Tsukuba, JP
Rajesh Khamankar - Irving TX
Shane R. Palmer - Dallas TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 218242

US Classification:

438253, 438239, 438240, 438241, 438242, 438254, 438255, 438256, 438397, 438398, 438399, 257905

Abstract:

An apparatus and method for fabrication a hexagonally symmetric cell, (e. g. , a dynamic random access memory cell ( )). The cell can comprise a bitline contact ( ), storage node contacts ( ) hexagonally surrounding the bitline contact ( ), storage nodes ( ) also surrounding the bitline contact ( ), a wordline ( ) portions of which form field effect transistor gates. Large distances between bitline contacts ( ) and storage node contact ( ) cause large problems during photolithography because dark areas are difficult to achieve when using Levenson Phaseshift. Because Levenson Phaseshift depends on wave cancellations between nearby features, commonly known as destructive interferences, the resultant printability of the pattern is largely a function of the symmetry and separation distances. When non-symmetries in the pattern occur, the result is weaker cancellations of fields (i. e. between features) and a large loss of image contrast and depth of focus during the printing step.

Temperature Spike For Uniform Nitridization Of Ultra-Thin Silicon Dioxide Layers In Transistor Gates

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US Patent:

6503846, Jan 7, 2003

Filed:

Jun 20, 2001

Appl. No.:

09/885587

Inventors:

Hiroaki Niimi - Richardson TX
James J. Chambers - Plano TX
Rajesh Khamankar - Coppell TX
Douglas T. Grider - McKinney TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 2131

US Classification:

438776, 438513, 438775, 438792

Abstract:

An embodiment of the present invention is a method of forming an ultra-thin dielectric layer, the method comprising the steps of: providing a substrate having a semiconductor surface; forming an oxygen-containing layer on the semiconductor surface; exposing the oxygen-containing layer to a nitrogen-containing plasma to create a uniform nitrogen distribution throughout the oxygen-containing layer; and re-oxidizing and annealing the layer to stabilize the nitrogen distribution, heal plasma-induced damage, and reduce interfacial defect density. This annealing step is selected from a group of four re-oxidizing techniques: Consecutive annealing in a mixture of H2 and N2 (preferably less than 20% H2), and then a mixture of O2 and N2 (preferably less than 20% O2); annealing by a spike-like temperature rise (preferably less than 1 s at 1000 to 1150Â C. ) in nitrogen-comprising atmosphere (preferably N2/O2 or N2O/H2); annealing by rapid thermal heating in ammonia of reduced pressure (preferably at 600 to 1000Â C. for 5 to 60 s); annealing in an oxidizer/hydrogen mixture (preferably N2O with 1% H2) for 5 to 60 s at 800 to 1050Â C.

Method Of Two-Step Annealing Of Ultra-Thin Silicon Dioxide Layers For Uniform Nitrogen Profile

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US Patent:

6548366, Apr 15, 2003

Filed:

Jun 20, 2001

Appl. No.:

09/885810

Inventors:

Hiroaki Niimi - Richardson TX
Douglas T. Grider - McKinney TX
Rajesh Khamankar - Coppell TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 2120

US Classification:

438384, 438287, 438786, 438787, 438142, 438762

Abstract:

Method For Forming Integrated Circuit Capacitor And Memory

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US Patent:

6555431, Apr 29, 2003

Filed:

Nov 16, 2000

Appl. No.:

09/712774

Inventors:

Guoqiang Xing - Dallas TX
Scott R. Summerfelt - Dallas TX
Rajesh Khamankar - Irving TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 218242

US Classification:

438253, 438118, 438396, 438397, 438398

Abstract:

A method for etching a feature in a platinum layer overlying a second material without substantially etching the second material. The method includes the the steps of: forming an adhesion-promoting layer between the platinum layer and the second material; forming a hardmask layer over the platinum layer; patterning and etching the hardmask layer in accordance with desired dimensions of the feature; and etching portions of the platinum layer not covered by the hardmask layer , the etching stopping on the adhesion-promoting layer. In further embodiments the adhesion-promoting and hardmask layers are TiâAlâN including at least 1% of aluminum.

Integrated Circuit Capacitor And Memory

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US Patent:

6600183, Jul 29, 2003

Filed:

Jun 26, 1998

Appl. No.:

09/105830

Inventors:

Mark R. Visokay - Dallas TX
Luigi Colombo - Dallas TX
Rajesh Khamankar - Irving TX
Mark A. Kressley - Richardson TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 2976

US Classification:

257295, 257310

Abstract:

An electrode structure for a capacitor. The electrode structure includes a contact plug comprising an oxidation barrier and a bottom electrode comprising a conductive adhesion-promoting portion and an oxidation-resistant portion , the adhesion-promoting portion contacting the oxidation barrier of the contact plug. In further embodiments, the oxidation barrier and adhesion-promoting portion comprise TiâAlâN.

Method For Uniform Nitridization Of Ultra-Thin Silicon Dioxide Layers In Transistor Gates

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US Patent:

6610614, Aug 26, 2003

Filed:

Jun 20, 2001

Appl. No.:

09/885695

Inventors:

Hiroaki Niimi - Richardson TX
Sunil Hattangady - McKinney TX
Rajesh Khamankar - Coppell TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H07L 21469

US Classification:

438775, 438287, 438513, 438516, 438517, 438723, 438762, 438763, 438766, 438770, 438774, 438776, 438777, 438787

Abstract:

A method of forming an ultra-thin dielectric layer, including the steps of: providing a substrate having a semiconductor surface; forming an oxygen-containing layer on the semiconductor surface; exposing the oxygen-containing layer to a nitrogen-containing plasma to create a uniform nitrogen distribution throughout the oxygen-containing layer; and re-oxidizing and annealing the layer to stabilize the nitrogen distribution, heal plasma-induced damage, and reduce interfacial defect density.

Method Of Ammonia Annealing Of Ultra-Thin Silicon Dioxide Layers For Uniform Nitrogen Profile

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US Patent:

6632747, Oct 14, 2003

Filed:

Jun 20, 2001

Appl. No.:

09/885600

Inventors:

Hiroaki Niimi - Richardson TX
Douglas T. Grider - McKinney TX
Rajesh Khamankar - Coppell TX
Sunil Hattangady - McKinney TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 2131

US Classification:

438775, 438763, 438769

Abstract:

An embodiment of the present invention is a method of forming an ultra-thin dielectric layer by providing a substrate having a semiconductor surface; forming an oxygen-containing layer on the semiconductor surface; exposing the oxygen-containing layer to a nitrogen-containing plasma to create a uniform nitrogen distribution throughout the oxygen-containing layer; and re-oxidizing and annealing the layer to stabilize the nitrogen distribution, heal plasma-induced damage, and reduce interfacial defect density. This annealing step is selected from a group of four re-oxidizing techniques: Consecutive annealing in a mixture of H2 and N2 (preferably less than 20% H2), and then a mixture of O2 and N2 (preferably less than 20% 02); annealing by a spike-like temperature rise (preferably less than 1 s at 1000 to 1150Â C. ) in nitrogen-comprising atmosphere (preferably N2/O2 or N2O/H2); annealing by rapid thermal heating in ammonia of reduced pressure (preferably at 600 to 1000Â C. for 5 to 60 s); annealing in an oxidizer/hydrogen mixture (preferably N2O with 1% H2) for 5 to 60 s at 800 to 1050Â C.

Semiconductor With A Nitrided Silicon Gate Oxide And Method

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US Patent:

6716695, Apr 6, 2004

Filed:

Dec 20, 2002

Appl. No.:

10/326188

Inventors:

Sunil V. Hattangady - McKinney TX
Jaideep Mavoori - Redmond WA
Che-Jen Hu - Plano TX
Rajesh B. Khamankar - Coppell TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 218242

US Classification:

438240, 438197, 438591, 438585, 438770, 438775

Abstract:

A method of fabricating a transistor includes providing a semiconductor substrate having a surface and forming a nitride layer outwardly of the surface of the substrate. The nitride layer is oxidized to form a nitrided silicon oxide layer comprising an oxide layer beneath the nitride layer. A high-K layer is deposited outwardly of the nitride layer, and a conductive layer is formed outwardly of the high-K layer. The conductive layer, the high-K layer, and the nitrided silicon oxide layer are etched and patterned to form a gate stack. Sidewall spacers are formed outwardly of the semiconductor substrate adjacent to the gate stack, and source/drain regions are formed in the semiconductor substrate adjacent to the sidewall spacers.

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