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Rajesh R Berigei

from Newark, CA
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Related to:
Bharati Berigei, 54
Connected to:
Felix Beriguete, 59Behzad J Beriji, 38Shruthi G Berikai, 50Timur Beriker, 53Susan M Berilla, 71Jackie Berillon, 89Anna N Berin, 43Charmaine R Berina, 48Nonna Berina, 68Roy F Berina, 67

Rajesh Berigei Phones & Addresses

  • Newark, CA

Resumes

Resumes

Rajesh Berigei Photo 1

Manager, Hardware Technology

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Location:
1141 Sterling Gate Dr, San Jose, CA 95120
Industry:
Computer Software
Work:
Apple
Manager, Hardware Technology
The Mathworks
Worldwide Semiconductor Manager
Texas Instruments Sep 2011 - Nov 2017
Senior Manager, Worldwide Electronic Design Automation
National Semiconductor Aug 2007 - Sep 2011
Director, System Design Technology and Cad
National Semiconductor Mar 1998 - Aug 2007
Senior Manager, Software and Eda Tool Integration
Education:
Unc Kenan - Flagler Business School 2017 - 2019
Master of Business Administration, Masters The University of Texas at Austin 1990 - 1992
Master of Science, Masters, Computer Engineering Pg Center, Kolar 1986 - 1990
Bachelor of Engineering, Bachelors, Electronics Engineering Umedbhai Patel English School
Ramaiah Institute of Technology
Bangalore University
Skills:
Asic
Embedded Systems
Ic
Fpga
Mixed Signal
Eda
Analog
Firmware
Pcb Design
Testing
Microcontrollers
System Architecture
Device Drivers
Power Management
Mobile Devices
C
Dft
Soc
Semiconductors
Debugging
Semiconductor Industry
Verilog
Electronics
Product Management
Integrated Circuits
Application Specific Integrated Circuits
Python
Numpy
Matplotlib
Support Vector Machines
Logistical Machine Learning
Deep Learning
Universal Verification Methodology
Systemverilog
Ni Labview
Ni Teststand
Matlab
Static Timing Analysis
Simplis
Javascript
Cmos
Integrated Circuit Design
Low Power Design
Primetime
Languages:
English
Hindi
Tamil
Marathi
Rajesh Berigei Photo 2

Rajesh Berigei

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Rajesh Berigei Photo 3

Rajesh Berigei

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Publications

Us Patents

Algorithmic Reactive Testbench For Analog Designs

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US Patent:
7853908, Dec 14, 2010
Filed:
Sep 5, 2007
Appl. No.:
11/899215
Inventors:
Jang Dae Kim - San Jose CA, US
Steve A. Martinez - Tucson AZ, US
Satya N. Mishra - Fort Collins CO, US
Alan P. Bucholz - Fort Collins CO, US
Hui X. Li - Antioch CA, US
Rajesh R. Berigei - San Jose CA, US
Assignee:
National Semiconductor Corporation - Santa Clara CA
International Classification:
G06F 17/50
G06F 9/45
US Classification:
716 5, 716 4, 716 6, 716 18, 703 3, 703 13, 703 14, 714740, 714741
Abstract:
An Algorithmic Reactive Testbench (ART) system is provided for the simulation/verification of an analog integrated circuit design. The ART system is a high level simulation/verification environment with a user program in which one or more analog testbenches are instantiated and operated as prescribed in an algorithmic reactive testbench program, and the properties of the unit testbenches (test objects) can be influenced by prior analysis of themselves or other tests. The test object may also contain various properties including information reflecting the status of the test object. The modification of a property of a test object is an act of communication in the ART system from the algorithmic reactive testbench program to the test object.

Dynamic Computation Of Esd Guidelines

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US Patent:
7558720, Jul 7, 2009
Filed:
Jan 9, 2006
Appl. No.:
11/328003
Inventors:
Rajesh R. Berigei - San Jose CA, US
Elroy Lucero - San Jose CA, US
Sury Maturi - San Jose CA, US
Marcel A. ter Beek - Pleasanton CA, US
Assignee:
National Semiconductor Corporation - Santa Clara CA
International Classification:
G06F 17/50
US Classification:
703 14, 716 5, 702117, 702118
Abstract:
An automated method for checking electrostatic discharge (ESD) guidelines ensures that a sufficient number of ESD protection cells have been provided in the neighborhood of each pad in an integrated circuit design to ensure adequate current sinking and voltage clamping during the occurrence of an ESD event.
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Rajesh R Berigei from Newark, CA Get Report