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Rajan P Konar

from San Jose, CA
Age ~45
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Also known as:
Konar Rajan, Konar Rojan
Phone and address:
3649 Mona Way, San Jose, CA 95130
Related to:
Melissa S Miller, 47Ruth H Wilson, 86
Connected to:
Ronald C Konar, 89Katie A Konarik, 34Linda A Konarik, 64Michael D Konarik, 57Angie L Konarski, 46Kimberly A Konarzewski, 57Michael S Konarzewski, 55Daniel A Konas, 73Aissatou Konate, 52Amadou Konate, 41

Rajan Konar Phones & Addresses

  • 3649 Mona Way, San Jose, CA 95130
  • Sunnyvale, CA
  • San Diego, CA
  • Austin, TX
  • Richardson, TX
  • 1269 Crestpoint Dr, San Jose, CA 95131

Work

Company: Apple Apr 1, 2014 Position: Senior asic engineer

Education

Degree: Master of Science, Masters School / High School: The University of Texas at Dallas 2002 to 2004 Specialities: Electrical Engineering

Skills

Asic • Functional Verification • Ic • Soc • Verilog • Integrated Circuit Design • Processors • Fpga • Rtl Design • Logic Design • Timing Closure • Static Timing Analysis • Systemverilog • Vlsi • Pcie • Vhdl • Perl • Debugging • Ncsim • Low Power Design • Dft • Rtl Coding • Primetime • Vmm • Tcl • Digital Electronics • Hardware Design • Digital Design • Vcs • Nc Verilog • Microcontrollers • Hardware Architecture • System on A Chip

Industries

Semiconductors

Resumes

Resumes

Rajan Konar Photo 1

Senior Asic Engineer

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Location:
San Jose, CA
Industry:
Semiconductors
Work:
Apple
Senior Asic Engineer
Amd Apr 2012 - Apr 2014
Member of Technical Staff
Broadcom Sep 2010 - Apr 2012
Ic Design Engineer
Marvell Semiconductor Dec 2006 - Sep 2010
Senior Asic Engineer
Freescale Semiconductor Mar 2005 - Dec 2006
Design Engineer
Education:
The University of Texas at Dallas 2002 - 2004
Master of Science, Masters, Electrical Engineering University of Mumbai 1996 - 2000
Bachelor of Engineering, Bachelors, Electronics Engineering, Electronics High School and Jr. College 1985 - 1996
Skills:
Asic
Functional Verification
Ic
Soc
Verilog
Integrated Circuit Design
Processors
Fpga
Rtl Design
Logic Design
Timing Closure
Static Timing Analysis
Systemverilog
Vlsi
Pcie
Vhdl
Perl
Debugging
Ncsim
Low Power Design
Dft
Rtl Coding
Primetime
Vmm
Tcl
Digital Electronics
Hardware Design
Digital Design
Vcs
Nc Verilog
Microcontrollers
Hardware Architecture
System on A Chip
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Rajan P Konar from San Jose, CA, age ~45 Get Report