Resumes
Resumes
Rahul Limaye Phones & Addresses
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4267 Churchill Dr, Pleasanton, CA 94588 (925) 997-0488
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Gilbert, AZ
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Livermore, CA
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2556 Sandhill Way, Santa Clara, CA 95051
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3650 Buckley St, Santa Clara, CA 95051
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Cupertino, CA
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San Jose, CA
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Mountain View, CA
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Alameda, CA
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Houghton, MI
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4267 Churchill Dr, Pleasanton, CA 94588
Publications
Us Patents
Power Supply Voltage Droop Compensated Clock Modulation For Microprocessors
View pageUS Patent:
7409568, Aug 5, 2008
Filed:
Jul 5, 2006
Appl. No.:
11/481717
Inventors:
Simon M. Tam - Redwood City CA, US
Rahul Limaye - Santa Clara CA, US
Utpal Desai - San Jose CA, US
Rahul Limaye - Santa Clara CA, US
Utpal Desai - San Jose CA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H03B 19/00
US Classification:
713322, 713300, 713310, 713320, 713321, 713323, 713324, 713330, 713340, 713401, 713600, 713601, 327114, 327361
Abstract:
A voltage source droop compensated clock modulation for microprocessors is described. Specifically, the circuit reduces the clock frequency if a voltage source droop is detected.
Power Supply Voltage Droop Compensated Clock Modulation For Microprocessors
View pageUS Patent:
20050022042, Jan 27, 2005
Filed:
Jul 25, 2003
Appl. No.:
10/627272
Inventors:
Simo Tam - Redwood City CA, US
Rahul Limaye - Santa Clara CA, US
Utpal Desai - San Jose CA, US
Rahul Limaye - Santa Clara CA, US
Utpal Desai - San Jose CA, US
International Classification:
G06F001/26
US Classification:
713323000
Abstract:
A voltage source droop compensated clock modulation for microprocessors is described. Specifically, the circuit reduces the clock frequency if a voltage source droop is detected.
Apparatus And Method For Performing Spread-Spectrum Clock Control
View pageUS Patent:
20140015578, Jan 16, 2014
Filed:
Sep 30, 2011
Appl. No.:
14/007538
Inventors:
Ewunnet Gebre-Selassie - San Jose CA, US
Dawson W. Kesling - Davis CA, US
Steven J. Kirch - Pleasanton CA, US
Rahul D. Limaye - Pleasanton CA, US
Shah M. Musa - Cupertino CA, US
Fugao Wang - San Jose CA, US
Dawson W. Kesling - Davis CA, US
Steven J. Kirch - Pleasanton CA, US
Rahul D. Limaye - Pleasanton CA, US
Shah M. Musa - Cupertino CA, US
Fugao Wang - San Jose CA, US
International Classification:
H03L 7/08
US Classification:
327157
Abstract:
A terminal includes control logic to control a phase-locked loop to output a spread-spectrum clocking signal. The control logic controls the generation of the spread-spectrum clocking signal by adjusting at least one parameter of the phase-locked loop. The parameter may be a charge pump setting or a loop-filter capacitance of the phase-locked loop, or their digital equivalents. Adjustment of the parameter reduces a predetermined portion of a communications spectrum. The predetermined portion may be located within a range of frequencies allocated to a specific channel, and reduction of the spectrum in this range may serve to reduce noise associated with clocking harmonics.