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Raghu Ram Kondapalli

from San Jose, CA
Age ~51
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Also known as:
Raghu R Kondapalli, Raghu Raghu Kondapalli, Raghu Ram Te Kondapalli, Raghu Te Kondapalli, Raghu B Kondapalli, Raghu T Kondapalli, Roghu Kondapalli, Kondapalli R Raghu
Phone and address:
2139 Terrena Valley Dr, San Jose, CA 95121
(408) 238-0329
Related to:
Sreerama BudarajuHema Budaraju, 50Sitamahal Budaraju, 77Sengee Kondapalli
Connected to:
Gopinath Kondapally, 47Goutham Kondapalli, 45Kiran K Kondapalli, 40Lavanya Kondapalli, 44Mohan H Kondapalli, 39Mridula Kondapalli, 38Pradeep Kondaparthi, 52Sreedutt S Kondapally, 50Srinivas Kondapalli, 37Srinivas R Kondapaneni, 57

Raghu Kondapalli Phones & Addresses

  • 2139 Terrena Valley Dr, San Jose, CA 95121 (408) 238-0329 (408) 238-4668
  • 2210 Terra Nova Ln, San Jose, CA 95121 (408) 238-4668
  • Merced, CA
  • Fremont, CA
  • Reno, NV
  • Sunnyvale, CA
  • Milpitas, CA
  • Santa Clara, CA
  • 2139 Terrena Valley Dr, San Jose, CA 95121

Work

Position: Building and Grounds Cleaning and Maintenance Occupations

Education

Degree: Bachelor's degree or higher

Resumes

Resumes

Raghu Kondapalli Photo 1

Data Center Group Chief Technology Officer Office

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Location:
San Francisco, CA
Industry:
Telecommunications
Work:
Intel Corporation
Data Center Group Chief Technology Officer Office
Appliedmicro Apr 2009 - Jun 2010
Senior Director of Technology
Cloud Grapes Apr 2009 - Jun 2010
Founder and Chief Technology Officer
Marvell Semiconductor Jan 2005 - Mar 2009
System Architect
Nokia 1999 - 2001
System Architect
Skills:
Asic
Embedded Systems
System Architecture
Soc
Wireless
Product Management
Device Drivers
Embedded Software
Semiconductors
Debugging
Architecture
Cloud Computing
Mobile Devices
Software Development
Systems Engineering
Distributed Systems
Digital Signal Processors
Network Architecture
Arm
Telecommunications
Raghu Kondapalli Photo 2

Raghu Kondapalli

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Publications

Us Patents

Flexible Port Rate Limiting

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US Patent:
7646718, Jan 12, 2010
Filed:
Oct 21, 2005
Appl. No.:
11/256465
Inventors:
Raghu Kondapalli - San Jose CA, US
Donald Pannell - Cupertino CA, US
Assignee:
Marvell International Ltd. - Hamilton
International Classification:
G01R 31/08
US Classification:
3702351, 370230
Abstract:
A switching device comprises M ports, N bandwidth tracking modules, a mapping memory, and a rate limiting module. The N bandwidth tracking modules each have an adjustable first threshold, an adjustable rate, and a fullness level, wherein M and N are integers that are greater than one. The mapping memory contains a map for each of the M ports, wherein each map assigns a set of the N bandwidth tracking modules to a corresponding one of the M ports, wherein each of the sets is individually modifiable to include zero to N of the N bandwidth tracking modules. The rate limiting module that selectively performs an action on a packet received at one of the M ports based on the fullness levels of the set of N bandwidth tracking modules identified by the map for the one of the M ports.

Floating Frame Timing Circuits For Network Devices

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US Patent:
7730230, Jun 1, 2010
Filed:
Dec 14, 2007
Appl. No.:
12/002029
Inventors:
Raghu Kondapalli - San Jose CA, US
Assignee:
Marvell International Ltd. - Hamilton
International Classification:
G06F 3/00
G06F 15/173
US Classification:
710 15, 710 16, 710 17, 710 18, 710 19, 710 29, 710 30, 709224
Abstract:
Apparatus having corresponding methods and computer programs comprise a plurality of interfaces to pass control frames; a memory to store configuration information; a select circuit to select one of the interfaces according to the configuration information; and a timing circuit to determine a time of passage of each control frame passing through the selected one of the interfaces.

Jitter Buffer For A Circuit Emulation Service Over An Internal Protocol Network

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US Patent:
7817545, Oct 19, 2010
Filed:
Sep 27, 2006
Appl. No.:
11/527596
Inventors:
Chi Fai Ho - Sunnyvale CA, US
Raghu R. Kondapalli - Sunnyvale CA, US
Lalit Merani - Santa Clara CA, US
Ravi Bail Bhat - Bangalore, IN
Prabhas Kejriwal - Palo Alto CA, US
Shashank Merchant - Santa Clara CA, US
Assignee:
Nokia Corporation - Espoo
International Classification:
H04J 1/16
H04L 12/66
H04L 12/28
US Classification:
370231, 370356, 370412
Abstract:
A jitter buffer receives a plurality of data packets comprising a circuit emulation service over internet protocol (CESIP), buffers the plurality of data packets, and plays data from the plurality of data packets at a constant bit rate corresponding to the CESIP.

Flexible Port Rate Limiting

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US Patent:
7873048, Jan 18, 2011
Filed:
Apr 26, 2006
Appl. No.:
11/411616
Inventors:
Raghu Kondapalli - San Jose CA, US
Assignee:
Marvell International Ltd. - Hamilton
International Classification:
H04L 12/28
US Classification:
370392, 709226
Abstract:
A switching device includes a parsing module, a classification module, a bandwidth tracking module, and a rate limitation module. The parsing module receives packets and separates layer four packets from the packets. The classification module classifies the layer four packets into control packets and data packets. The bandwidth tracking module communicates with the classification module and has a fullness level. The rate limitation module selectively performs an action on at least one of the control packets and data packets based on the fullness level. The action includes at least one of discarding, asserting flow control, and accepting the at least one of the control packets and data packets.

Message Processing

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US Patent:
7876686, Jan 25, 2011
Filed:
Nov 24, 2008
Appl. No.:
12/276955
Inventors:
Raghu Kondapalli - San Jose CA, US
Assignee:
Marvell International, Ltd.
International Classification:
H04J 3/14
US Classification:
3702351
Abstract:
Devices, systems, methods, and other embodiments associated with message processing are described. In one embodiment, an apparatus includes an interaction logic to interact with a message associated with an isochronous stream. The message is associated with a class of information provided on the isochronous stream. The apparatus includes a history logic to monitor messages associated with the class of information. The history logic determines a class history for the class of information. The apparatus includes a process logic to selectively process the message based on the class history.

Packet Sampling Using Rate-Limiting Mechanisms

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US Patent:
8036113, Oct 11, 2011
Filed:
Jul 6, 2007
Appl. No.:
11/825556
Inventors:
Raghu Kondapalli - San Jose CA, US
Assignee:
Marvell International Ltd. - Hamilton
International Classification:
H04L 12/26
US Classification:
370230, 370235
Abstract:
Apparatus having related methods and computer programs comprises an input circuit and one or more output circuits; a forwarding engine to transfer packets to the output circuits; and a rate limiting circuit to selectively pass packets from the input circuit to the forwarding engine, the rate limiting circuit comprising a counter to keep a count, an increment circuit to increment the count when the input circuit receives a packet, a decrement circuit to decrement the count by a decrement amount, an action circuit to perform action(s) based on the count and count threshold(s), and a configuration register to store a sampling flag, wherein when the sampling flag is set, the decrement amount is set to zero and the actions include sending a packet to a predetermined destination, and setting the count to zero, when the count exceeds a count threshold.

Floating Frame Timing Circuits For Network Devices

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US Patent:
8166216, Apr 24, 2012
Filed:
Apr 20, 2011
Appl. No.:
13/090623
Inventors:
Raghu Kondapalli - San Jose CA, US
Assignee:
Marvell International Ltd. - Hamilton
International Classification:
G06F 3/00
G06F 1/12
G06F 1/04
G06F 15/16
US Classification:
710 58, 710 5, 710 36, 710 52, 713400, 713500, 713600, 709230
Abstract:
A networking device includes a network port configured to receive a message from a remote networking device. The network port includes a detector configured to detect reception of the message. A queue controller is configured to integrate a timestamp with the message to generate a modified message. An ingress timer is configured to generate the timestamp based on an arrival time of the message at the network port.

Rendering A Video Stream Based On Digital Clock Generated Based On Timing Information

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US Patent:
8341454, Dec 25, 2012
Filed:
Dec 15, 2008
Appl. No.:
12/334796
Inventors:
Raghu Kondapalli - San Jose CA, US
Assignee:
Marvell International Ltd.
International Classification:
G06F 1/04
G06F 1/12
G06F 1/00
US Classification:
713600, 713400, 713500
Abstract:
Systems, methods, and other embodiments associated with clock generation are provided. In one embodiment, a precise timing protocol message is parsed to extract timing information. Timing waveform parameters are calculated based on the timing information and a digital clock is generated based on the waveform parameters. A video stream can then be decoded and rendered, where the rendering depends on the digital clock.
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Raghu Ram Kondapalli from San Jose, CA, age ~51 Get Report