Resumes
Resumes
Qimeng Zhou Phones & Addresses
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1682 Meadowlark Ln, Sunnyvale, CA 94087 (408) 733-7975
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Santa Clara, CA
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San Jose, CA
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Las Vegas, NV
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San Francisco, CA
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1682 Meadowlark Ln, Sunnyvale, CA 94087 (408) 242-5275
Work
Position:
Professional/Technical
Education
Degree:
Graduate or professional degree
Emails
Publications
Us Patents
Method Of Programming A Memory Cell To Contain Multiple Values
View pageUS Patent:
58319018, Nov 3, 1998
Filed:
Nov 8, 1996
Appl. No.:
8/745596
Inventors:
Yuan Tang - San Jose CA
Qimeng Zhou - Santa Clara CA
Hsingya Arthur Wang - Saratoga CA
Qimeng Zhou - Santa Clara CA
Hsingya Arthur Wang - Saratoga CA
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
G11C 1134
US Classification:
36518503
Abstract:
A method for programming multiple values in an individual flash memory cell is disclosed. An individual flash cell is programmed by holding the bit line, corresponding to the particular memory cell to a value, V. sub. d, while the voltage on the control gate, V. sub. g, of the memory cell is varied. By varying the voltage on the control gate, multiple values are stored in the memory cell. The resulting values are self-convergent, therefore, verify circuitry becomes unnecessary.
Block Select Transistor And Method Of Fabrication
View pageUS Patent:
57633070, Jun 9, 1998
Filed:
Nov 8, 1996
Appl. No.:
8/745278
Inventors:
Hsingya Arthur Wang - Saratoga CA
Qimeng Zhou - Santa Clara CA
Qimeng Zhou - Santa Clara CA
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
H01L 218247
US Classification:
438258
Abstract:
A flash memory device having a reduced area is disclosed. The device uses a polyI layer to act as a select transistor for the memory cells comprising the core array. Also, a ground plate is used to isolate the areas of the memory array where high voltage devices should not be located, thereby allowing peripheral components to be fabricated in the core array area. Also disclosed is a polyII layer used to access two sublines controlling two different sectors of the memory array architecture. By using such a layout, die space savings is attained.
Bit Line Discharge Method For Reading A Multiple Bits-Per-Cell Flash Eeprom
View pageUS Patent:
57544751, May 19, 1998
Filed:
Jun 27, 1997
Appl. No.:
8/884547
Inventors:
Colin Bill - Cupertino CA
Ravi Gutala - Sunnyvale CA
Qimeng (Derek) Zhou - Sunnyvale CA
Jonathan Su - Sunnyvale CA
Ravi Gutala - Sunnyvale CA
Qimeng (Derek) Zhou - Sunnyvale CA
Jonathan Su - Sunnyvale CA
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
G11C 1134
US Classification:
36518525
Abstract:
An improved reading structure (110) for performing a read operation in an array of multiple bits-per-cell flash EEPROM memory cells is provided. A memory core array (12) includes a plurality of memory cells, each being previously programmed to one of a plurality of memory conditions defined by memory core threshold voltages. A reference cell array (22) includes a plurality of reference core cells which are selected together with a selected core cell and provides selectively one of a plurality of reference cell bit line voltages defined by reference cell threshold voltages. Each of the reference cells are previously programmed at the same time as when the memory core cells are being programmed. A precharge circuit (36) is used to precharge the array bit lines and the reference bit lines to a predetermined potential. A detector circuit (28) is responsive to the bit line voltages of the reference cells for generating strobe signals.
Supply Voltage-Independent Reference Voltage Circuit
View pageUS Patent:
59558741, Sep 21, 1999
Filed:
Jun 23, 1994
Appl. No.:
8/265583
Inventors:
Qimeng Zhou - Sunnyvale CA
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
G05F 302
US Classification:
323315
Abstract:
A reference voltage circuit is disclosed that is independent of the voltage supply as well as substantially insensitive to process and temperature variations. The reference voltage circuit includes an intrinsic transistor circuit which includes a plurality of intrinsic transistors of equal size. The intrinsic transistor circuit is coupled to a current mirror circuit, and a plurality of threshold transistors. In so doing, a reference voltage circuit is provided that is substantially independent of process and temperature variations. In addition, by grounding the source connections of the plurality of threshold transistors, the reference voltage circuit output voltage also is substantially independent of supply voltage variations.