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Priya N Vaidya

from Shrewsbury, MA
Age ~50
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Also known as:
Priya N Nmcsa, Prya Vaidya
Phone and address:
25 Stonybrook Ln, Shrewsbury, MA 01545
(508) 333-3024
Related to:
Sharyo N Vaidya, 46Jyoti N Vaidya
Connected to:
Aaditya H Vaidya, 40Advait S Vaidya, 37Akash H Vaidya, 31Ayushma Vaidya, 39Bakulesh C Vaidya, 69Bhalchandra Vaidya, 77Chaitanya Vaidya, 84Chitra Vaidya, 72Deepak Vaidya, 69Ekta K Vaidya, 47

Priya Vaidya Phones & Addresses

  • 25 Stonybrook Ln, Shrewsbury, MA 01545 (508) 333-3024
  • 308 Spring St, Shrewsbury, MA 01545 (508) 845-9516
  • 632 Warren Wright Rd, Belchertown, MA 01007 (413) 256-2349
  • 623 Warren Wright Rd, Belchertown, MA 01007

Work

Company: Sardar patel vidyalaya Jul 2000 Position: Head of the department of social science

Education

School / High School: IGNOU 2000

Resumes

Resumes

Priya Vaidya Photo 1

Software Power And Performance Optimization

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Location:
Shrewsbury, MA
Industry:
Computer Software
Work:
Marvell Semiconductor Nov 2006 - Mar 2010
Software Architect
Intel Corporation Nov 2006 - Mar 2010
Software Power and Performance Optimization
Intel Corporation May 2000 - Nov 2006
Software Architect
Education:
University of Massachusetts Amherst 1998 - 2000
Master of Science, Masters, Electrical Engineering Indian Institute of Technology, Bombay 1998
Masters, Master of Technology
Skills:
Processors
Embedded Systems
Software Engineering
Hardware Architecture
Soc
Arm
Algorithms
Debugging
Low Power Design
Computer Architecture
Linux
Firmware
Linux Kernel
Device Drivers
Signal Processing
Software Development
Languages:
English
Hindi
Marathi
Priya Vaidya Photo 2

Priya Vaidya

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Priya Vaidya Photo 3

Priya Vaidya

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Work:
SARDAR PATEL VIDYALAYA

Jul 2000 to 2000
Head of the department of Social Science
Priya Vaidya Photo 4

Priya Vaidya

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Publications

Us Patents

Least Mean Square Dynamic Cache-Locking

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US Patent:
7266646, Sep 4, 2007
Filed:
Aug 8, 2006
Appl. No.:
11/501490
Inventors:
Priya N. Vaidya - Shrewsbury MA, US
Moinul H. Khan - Austin TX, US
Assignee:
Marvell International Ltd. - Hamilton
International Classification:
G06F 12/12
US Classification:
711133, 711145, 711152, 711163
Abstract:
A dynamic cache-locking algorithm may determine the most frequently used function(s) and the number of cache lines that should be locked into the instruction cache embedded into a processor. By evaluating the dynamic cache-locking algorithm, a determination may be made to lock an optimal amount of functions that correspond to a given, limited amount of instruction cache.

System And Method For Adaptive Power Management

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US Patent:
7346787, Mar 18, 2008
Filed:
Dec 7, 2004
Appl. No.:
11/006917
Inventors:
Priya N Vaidya - Shrewsbury MA, US
Premanand Sakarda - Acton MA, US
Bryan C Morgan - Leominster MA, US
Yi Ge - Westborough MA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 1/00
US Classification:
713300, 713322, 713324
Abstract:
A disclosed method involves initializing a performance profiler of a processing system. The performance profiler may include performance profile parameters for a power management policy for the processing system. The method also involves retrieving performance metrics for the processing system from a performance monitoring unit (PMU) of the processing system, in response to a determination that performance details should be collected. A current performance state of the processing system may be determined, based at least in part on the performance profile parameters and the performance metrics from the PMU. The current performance state may then be communicated to a policy manager of the processing system. Other embodiments are disclosed and claimed.

System And Method For Adaptive Power Management Based On Processor Utilization And Cache Misses

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US Patent:
7814485, Oct 12, 2010
Filed:
Dec 7, 2004
Appl. No.:
11/007098
Inventors:
Bryan C Morgan - Leominster MA, US
Premanand Sakarda - Acton MA, US
Priya N Vaidya - Shrewsbury MA, US
Yi Ge - Westborough MA, US
Zhou Gao - Shanghai, CN
Manoj I Thadani - Marlborough MA, US
Canhui Yuan - Shanghai, CN
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 9/46
G06F 1/00
US Classification:
718100, 713323
Abstract:
A processing system may include a performance monitoring unit (PMU), a machine accessible medium, and a processor responsive to the PMU and the machine accessible medium. Instructions encoded in the machine accessible medium, when executed by the processor, may determine whether performance details for the processing system should be collected, based at least in part on a predetermined monitoring policy for the processing system. The instructions may generate performance data for the processing system, based at least in part on data obtained from the PMU. The instructions may determine whether the processing system should be reconfigured, based at least in part on the performance data and a power policy profile for the processing system. The instructions may automatically adjust power consumption of the processing system by using the PMU to reconfigure the processing system. Other embodiments are described and claimed.

Power Management In Electronic Systems

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US Patent:
7971084, Jun 28, 2011
Filed:
Dec 28, 2007
Appl. No.:
12/006064
Inventors:
Bryan C. Morgan - Leominster MA, US
Priya N. Vaidya - Shrewsbury MA, US
Premanand Sakarda - Acton MA, US
Marlon A. Moncrieffe - Leominster MA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 1/32
US Classification:
713323, 713320, 710 22, 710 28
Abstract:
In one embodiment, an electronic apparatus comprises at least one processor and a computer readable medium coupled to the processor and comprising logic instructions encoded in the computer readable medium, wherein the instructions, when executed in a processing system, cause the processing system to perform operations comprising initializing a direct memory access profiler in an electronic system, wherein the direct memory access is coupled to a policy manager in the electronic system, measuring at least one memory consumption characteristic of the electronic system, communicating the at least one memory consumption characteristic to a policy manager of the electronic system, and using the at least one memory consumption characteristic to adjust a power state of the electronic system.

Systems And Methods For Reducing Display Under-Run And Conserving Power

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US Patent:
8125490, Feb 28, 2012
Filed:
Jul 9, 2008
Appl. No.:
12/170330
Inventors:
Priya Vaidya - Shrewsbury MA, US
Kalpana Mittal - Sturbridge MA, US
Assignee:
Marvell International Ltd.
International Classification:
G06F 13/14
G06T 1/00
G06T 15/00
US Classification:
345520, 345503, 345522
Abstract:
A display system is disclosed. The display system has a processor, a memory, a display device, a display controller configured to control the display device, and a bus connecting the processor, the memory, and the display controller. The display system also has a performance monitoring module configured to monitor events that occur on the bus during operation of the display system, and a performance profiling module configured to calculate, based on the monitored events, an available throughput of the processor on the bus. The display system also has a policy manager module configured to determine a refresh rate for the display controller such that a throughput on the bus required by the display controller is less than the calculated available throughput.

Method And System For Selecting An Operating Frequency For A Chip To Provide A Desired Overall Power Dissipation Value For The Chip

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US Patent:
8281160, Oct 2, 2012
Filed:
Mar 9, 2009
Appl. No.:
12/400604
Inventors:
Yu Bai - Worcester MA, US
Priya Vaidya - Shrewsbury MA, US
Premanand Sakarda - Acton MA, US
Assignee:
Marvell International Ltd. - Hamilton
International Classification:
G06F 1/00
US Classification:
713300
Abstract:
Methods, apparatus, and computer program products for implementing power management within Systems on Chips (SOCs). The method includes selecting an operating frequency for a chip from an operating frequency point set that provides a desired overall power dissipation value.

Power Management In Electronic Systems

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US Patent:
8402293, Mar 19, 2013
Filed:
Jun 28, 2011
Appl. No.:
13/171157
Inventors:
Bryan C. Morgan - Leominster MA, US
Priya N. Vaidya - Shrewsbury MA, US
Premanand Sakarda - Acton MA, US
Marlon A. Moncrieffe - Leominster MA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 1/32
US Classification:
713323, 713320, 710 22, 710 28
Abstract:
In one embodiment, an electronic apparatus comprises at least one processor and a computer readable medium coupled to the processor and comprising logic instructions encoded in the computer readable medium, wherein the instructions, when executed in a processing system, cause the processing system to perform operations comprising initializing a direct memory access profiler in an electronic system, wherein the direct memory access is coupled to a policy manager in the electronic system, measuring at least one memory consumption characteristic of the electronic system, communicating the at least one memory consumption characteristic to a policy manager of the electronic system, and using the at least one memory consumption characteristic to adjust a power state of the electronic system.

Method And System For Selecting An Operating Frequency For A Chip To Provide A Desired Overall Power Dissipation Value For The Chip

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US Patent:
8578188, Nov 5, 2013
Filed:
Oct 2, 2012
Appl. No.:
13/633679
Inventors:
- Hamilton, BM
Priya Vaidya - Shrewsbury MA, US
Premanand Sakarda - Acton MA, US
Assignee:
Marvell International Ltd. - Hamilton
International Classification:
G06F 1/00
US Classification:
713300
Abstract:
Methods, apparatus, and computer program products for implementing power management within Systems on Chips (SOCs). The method includes selecting an operating frequency for a chip from an operating frequency point set that provides a desired overall power dissipation value.
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Priya N Vaidya from Shrewsbury, MA, age ~50 Get Report