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Prasanna Kumar Balasundaram

from San Diego, CA
Age ~44
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Also known as:
Prasanna K Balasundaram, Kuma Balasundaram Prasannakum
Phone and address:
16113 Falcon Crest Dr, San Diego, CA 92127
Related to:
Vinoth Kumar Deivasigamani, 43Thangavel DeivasigamaniLavanya Loganathan, 43Sabitha Loganathan
Connected to:
Brenda A Balasuriya, 82Devaka N Balasuriya, 43Laura C Balasus, 85Adamu Balat, 40Nereo V Balatayo, 39Michael B Balatbat, 31David Balatero, 38Stephen R Balatine, 76Terry K Balatsias, 61Jennifer L Balauro, 50

Prasanna Balasundaram Phones & Addresses

  • 16113 Falcon Crest Dr, San Diego, CA 92127
  • 12495 Caminito Brioso, San Diego, CA 92131
  • 8332 Regents Rd, San Diego, CA 92122 (858) 412-5795
  • 4634 Hagadorn Rd, East Lansing, MI 48823 (517) 332-1948
  • 4642 Hagadorn Rd, East Lansing, MI 48823 (517) 664-1677
  • La Jolla, CA

Work

Company: Amd Jan 2020 Position: Principal member of technical staff

Education

Degree: Master of Science, Masters School / High School: Michigan State University 2001 to 2003 Specialities: Computer Engineering

Skills

San • Nas • Storage

Industries

Telecommunications

Resumes

Resumes

Prasanna Balasundaram Photo 1

Principal Member Of Technical Staff

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Location:
San Diego, CA
Industry:
Telecommunications
Work:
Amd
Principal Member of Technical Staff
Qualcomm
Engineer
Education:
Michigan State University 2001 - 2003
Master of Science, Masters, Computer Engineering
Skills:
San
Nas
Storage

Publications

Us Patents

Associating Data For Events Occurring In Software Threads With Synchronized Clock Cycle Counters

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US Patent:
20100299668, Nov 25, 2010
Filed:
May 19, 2009
Appl. No.:
12/468114
Inventors:
Suresh K. Venkumahanti - Austin TX, US
Robert Shuicheong Chan - Chula Vista CA, US
Prasanna Kumar Balasundaram - San Diego CA, US
Louis Achille Giannini - Berwyn IL, US
Assignee:
QUALCOMM INCORPORATED - San Diego CA
International Classification:
G06F 9/46
US Classification:
718102
Abstract:
Methods, apparatuses, and computer-readable storage media are disclosed for reducing power by reducing hardware-thread toggling in a multi-processor. In a particular embodiment, a method is disclosed that includes collecting data from a plurality of software threads being processed by a processor, where the data for each of the events includes a value of an associated clock cycle counter upon occurrence of the event. Data is correlated for the events occurring for each of the plurality of threads by starting each of a plurality of clock cycle counters associated with the software threads at a common time. Alternatively, data is correlated for the events by logging a synchronizing event within each of the plurality of software threads.

Interleaved Architecture Tracing And Microarchitecture Tracing

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US Patent:
20130073910, Mar 21, 2013
Filed:
Sep 20, 2011
Appl. No.:
13/237071
Inventors:
Suresh K. Venkumahanti - Austin TX, US
Prasanna Kumar Balasundaram - San Diego CA, US
Robert A. Lester - Austin TX, US
Assignee:
QUALCOMM INCORPORATED - San Diego CA
International Classification:
G06F 11/30
US Classification:
714 45, 714E11179
Abstract:
Systems and method for embedded trace macrocell (ETM) devices configured to dynamically interleave architecture/program tracing with microarchitecture/hardware tracing. An ETM device includes logic to enable interleaved program tracing and hardware state sampling. A core interface is configured to receive program trace and hardware state information of a microprocessor and a combining module is configured to interleave the program trace and hardware state information. A packet generation module may be configured to packetize the program trace and hardware state information into packets at operational speeds of the microprocessor.
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Prasanna Kumar Balasundaram from San Diego, CA, age ~44 Get Report