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Prabha K Atluri

from Allen, TX
Age ~48
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Also known as:
Prabha Krishna Atluri, Prabha K Altluri, Prabha K Alturi, Prabha A Bolnedi
Related to:
Srikanth Bolnedi, 55
Connected to:
Charita Atluri, 40Dinesh K Atluri, 35Hima S Atluri, 58Kumar Atluri, 48Murali K Atluri, 54Neela R Atluri, 63Prasant Atluri, 52Sanjeev R Atluri, 40Satish Atluri, 55Adam Atmaca, 37

Prabha Atluri Phones & Addresses

  • Allen, TX
  • Fishkill, NY
  • 4567 Cape Charles Dr, Plano, TX 75024
  • 2001 Spring Creek Pkwy, Plano, TX 75074
  • Corvallis, OR
  • Dallas, TX

Resumes

Resumes

Prabha Atluri Photo 1

Senior Design Engineer

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Location:
1714 San Jacinto Dr, Allen, TX 75013
Industry:
Wireless
Work:
Drs Technologies, Inc.
Senior Design Engineer
Tektronix Communications
Hardware Design Engineer
L-3 Communications Nov 2009 - Aug 2012
Fpga Design Engineer
Syndiant, Inc Nov 2008 - Nov 2009
Lead Verification Engineer
Texas Instruments Oct 2000 - Oct 2008
Design Engineer
Education:
Oregon State University 1998 - 2000
Master of Science, Masters Andhra University
Bachelors, Bachelor of Science, Electronics Engineering
Skills:
Verilog
Vhdl
Xilinx
Formal Verification
Asic
Hardware Architecture
Timing Closure
Prabha Atluri Photo 2

Prabha Atluri

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Publications

Us Patents

Preemptive Rendering Arbitration Between Processor Hosts And Display Controllers

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US Patent:
20060022985, Feb 2, 2006
Filed:
Jul 30, 2004
Appl. No.:
10/903750
Inventors:
Thomas Shepherd - McKinney TX, US
Minh Chau - Carrollton TX, US
Prabha Atluri - Plano TX, US
Sang-Won Song - Plano TX, US
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
G06F 13/18
G09G 5/36
US Classification:
345535000, 345558000
Abstract:
A system comprises a display controller adapted to monitor a first-in, first-out module (“FIFO”) data level, a memory controller coupled to said display controller, and a memory coupled to said display controller and said memory controller. The memory controller permits the display controller to immediately access the memory when the FIFO data level drops below a pre-determined threshold level and no display panel horizontal or vertical blanking periods are in progress.

Multi-Threaded Dma

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US Patent:
20060080478, Apr 13, 2006
Filed:
Mar 17, 2005
Appl. No.:
11/082564
Inventors:
Franck Seigneret - Roquefort les pins, FR
Sivayya Ayinala - Plano TX, US
Nabil Khalifa - Saint Laurent du Van, FR
Praveen Kolli - Dallas TX, US
Prabha Atluri - Plano TX, US
International Classification:
G06F 13/28
US Classification:
710022000
Abstract:
A direct memory access (DMA) circuit () includes a read port () and a write port (). The DMA circuit () is a multithreaded initiator with “m” threads on the read port () and “n” threads on the write port (). The DMA circuit () includes two decoupled read and write contexts and schedulers () that provide for more efficient buffering and pipelining. The schedulers () are mainly arbitrating between channels at a thread boundary. One thread is associated to one DMA service where a service can be a single or burst transaction. The multithreaded DMA transfer allows for concurrent channel transfers.
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Prabha K Atluri from Allen, TX, age ~48 Get Report