Phillip Gregory Wald

RE37505, Jan 15, 2002

Apr 5, 1996

08/628287

Guy Blalock - Boise ID
Phillip G. Wald - Boise ID

Micron Technology, Inc. - Boise ID

H01L 2978

257309, 257303

A method of forming a capacitor on a semiconductor wafer includes: a) in a dry etching reactor, selectively anisotropically dry etching a capacitor contact opening having a minimum selected open dimension into an insulating dielectric layer utilizing selected gas flow rates of a reactive gas component and an inert gas bombarding component, the flow rate of the bombarding component significantly exceeding the flow rate of the reactive component to effectively produce a capacitor contact opening having grooved striated sidewalls and thereby defining female capacitor contact opening striations; b) providing a layer of an electrically conductive storage node material within the striated capacitor contact opening; c) removing at least a portion of the conductive material layer to define an isolated capacitor storage node within the insulating dielectric having striated sidewalls; d) etching the insulating dielectric layer selectively relative to the conductive material sufficiently to expose at least a portion of the external male striated conductive material sidewalls; and e) providing conformal layers of capacitor dielectric and capacitor cell material atop the etched conductive material and over its exposed striated sidewalls. The invention also includes a stacked capacitor construction having an electrically conductive storage node with upwardly rising external sidewalls. Such sidewalls have longitudinally extending striations to maximize surface area and corresponding capacitance in a resulting construction.

6352946, Mar 5, 2002

Feb 24, 1999

09/256634

Richard H. Lane - Boise ID
Phillip G. Wald - Boise ID

Micron Technology, Inc. - Boise ID

H01L 2170

438795, 438904, 438660, 257297

This invention embodies an improved process for annealing integrated circuits to repair fabrication-induced damage. An integrated circuit is annealed in a pressurized sealed chamber in which a forming gas comprising hydrogen is present. Pressurization of the chamber reduces the contribution made by the final anneal step to total thermal exposure by increasing the diffusion rate of the hydrogen into the materials from which the integrated circuit is fabricated. Ideally, the forming gas contains, in addition to hydrogen, at least one other gas such as nitrogen or argon that will not react with hydrogen and, thus, reduce the danger of explosion. However, the integrated circuit may be annealed in an ambiance containing only hydrogen gas that is maintained at a pressure greater than ambient atmospheric pressure.

6383887, May 7, 2002

Nov 28, 2000

09/724752

Kunal R. Parekh - Boise ID
John K. Zahurak - Boise ID
Phillip G. Wald - Boise ID

Micron Technology, Inc. - Boise ID

H01L 2120

438396, 438255

The invention includes a number of methods and structures pertaining to semiconductor circuit technology, including: methods of forming DRAM memory cell constructions; methods of forming capacitor constructions; DRAM memory cell constructions; capacitor constructions; and monolithic integrated circuitry. The invention includes a method of forming a capacitor comprising the following steps: a) forming a mass of silicon material over a node location, the mass comprising exposed doped silicon and exposed undoped silicon; b) substantially selectively lo forming rugged polysilicon from the exposed undoped silicon and not from the exposed doped silicon; and c) forming a capacitor dielectric layer and a complementary capacitor plate proximate the rugged polysilicon and doped silicon. The invention also includes a capacitor comprising: a) a first capacitor plate; b) a second capacitor plate; c) a capacitor dielectric layer intermediate the first and second capacitor plates; and d) at least one of the first and second capacitor plates comprising a surface against the capacitor dielectric layer and wherein said surface comprises both doped rugged polysilicon and doped non-rugged polysilicon.

6387828, May 14, 2002

Aug 31, 2000

09/654029

Richard H. Lane - Boise ID
Phillip G. Wald - Boise ID

Micron Technology, Inc. - Boise ID

H01L 21283

438795, 438660, 438661, 438663, 438904

This invention embodies an improved process for annealing integrated circuits to repair fabrication-induced damage. An integrated circuit is annealed in a pressurized sealed chamber in which a forming gas comprising hydrogen is present. Pressurization of the chamber reduces the contribution made by the final anneal step to total thermal exposure by increasing the diffusion rate of the hydrogen into the materials from which the integrated circuit is fabricated. Ideally, the forming gas contains, in addition to hydrogen, at least one other gas such as nitrogen or argon that will not react with hydrogen and, thus, reduce the danger of explosion. However, the integrated circuit may be annealed in an ambiance containing only hydrogen gas that is maintained at a pressure greater than ambient atmospheric pressure.

6391805, May 21, 2002

Aug 31, 2000

09/653120

Richard H. Lane - Boise ID
Phillip G. Wald - Boise ID

Micron Technology, Inc. - Boise ID

C23F 100

438795, 438660, 438663, 438904, 257297, 257651

This invention embodies an improved process for annealing integrated circuits to repair fabrication-induced damage. An integrated circuit is annealed in a pressurized sealed chamber in which a forming gas comprising hydrogen is present. Pressurization of the chamber reduces the contribution made by the final anneal step to total thermal exposure by increasing the diffusion rate of the hydrogen into the materials from which the integrated circuit is fabricated. Ideally, the forming gas contains, in addition to hydrogen, at least one other gas such as nitrogen or argon that will not react with hydrogen and, thus, reduce the danger of explosion. However, the integrated circuit may be annealed in an ambiance containing only hydrogen gas that is maintained at a pressure greater than ambient atmospheric pressure.

6407455, Jun 18, 2002

Jul 10, 2000

09/612677

Phillip G. Wald - Boise ID
Kunal R. Parekh - Boise ID

Micron Technology, Inc. - Boise ID

H01L 2352

257774, 257775, 257776

A semiconductor device including a structure having an upper surface and an contact surface formed at the upper surface of the structure. An insulating material is formed over the contact surface and a conductive runner extends over the active area such that a lower surface of the conductive runner is above and separated from the active area. A widened portion is formed in the conductive runner with an opening formed in the widened portion and self-aligned to edges of the widened portion. A conductive pillar is self-aligned to the opening and extends downward through the opening, through the insulating material, to the active area. The conductive runner provides local interconnection that can be routed over device features formed in and on the structure without using an additional metal layer.

6455400, Sep 24, 2002

Jun 13, 2000

09/596237

Keith Smith - Boise ID
Phillip G. Wald - Boise ID

Micron Technology, Inc. - Boise ID

H01L 2120

438482

In one aspect, the invention includes a semiconductor processing method comprising depositing a silicon layer over a substrate at different deposition temperatures which at least include increasing the deposition temperature through a range of from about 550Â C. to about 560Â C. In another aspect, the invention includes a semiconductor processing method comprising, in an uninterrupted deposition process, depositing a silicon layer which comprises an essentially amorphous silicon region, an essentially polycrystalline silicon region, and a transition region interconnecting the essentially amorphous silicon region and the essentially polycrystalline silicon region, the essentially amorphous silicon region having an amorphous silicon content which is greater than or equal to about 90 weight percent of a total material of the amorphous silicon region, the essentially polycrystalline silicon region having a polycrystalline silicon content which is greater than or equal to about 90 weight percent of a total material of the polycrystalline silicon region, the transition comprising an amorphous silicon content and a polycrystalline silicon content, the transition region being defined as a region having both a lower amorphous silicon content than the essentially amorphous silicon region and a lower polycrystalline silicon content than the essentially polycrystalline silicon region, the transition region being at least 45 Angstroms thick.

6472328, Oct 29, 2002

Jun 29, 2001

09/896773

Terry Gilton - Boise ID
Casey Kurth - Eagle ID
Russ Meyer - Boise ID
Phillip G. Wald - Boise ID

Micron Technology, Inc. - Boise ID

H01L 21302

438705, 438301, 438303, 438305, 438308, 438953, 438753, 438704, 438723, 438696, 134 13

A method of forming an electrical contact to semiconductive material includes forming an insulative layer over a contact area of semiconductive material. A contact opening is etched through the insulative layer to the semiconductive material contact area. Such etching changes an outer portion of the semiconductive material exposed by the etching. The change is typically in the form of modifying crystalline structure of only an outer portion from that existing prior to the etch. The changed outer portion of the semiconductive material is etched substantially selective relative to semiconductive material therebeneath which is unchanged. The preferred etching chemistry is a tetramethyl ammonium hydroxidde solution. A conductive material within the contact opening is formed in electrical connection with the semiconductive material. In another aspect, the changed outer portion is etched with a basic solution regardless of selectivity in the etch relative to semiconductive material therebeneath which is unchanged by the contact opening etch.