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Peter C Vandervoorn

from Rochester, NY
Age ~85
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Also known as:
Peter J Vandervoorn, Pter C Vandervoorn, Peter C Voorn, Vandervoorn Peter
Phone and address:
26 Tartarian Cir, Rochester, NY 14612
(585) 225-9496
Related to:
Brenda S Poley, 76Cindy Glazier, 60Karen Poley, 56Timothy Poley, 76Gerard Sybers
Connected to:
Aaron V Vanderweele, 48Adam J Vanderwijst, 40Adrean R Vanderwilt, 52Alexis Vanderveen, 56Amanda B Vanderway, 36Amber D Vanderwal, 34Amy M Vandervest, 54Amy L Vanderwater, 54Andrew L Vanderwoude, 35Andy Vanderwoude, 73

Peter Vandervoorn Phones & Addresses

  • 26 Tartarian Cir, Rochester, NY 14612 (585) 225-9496
  • Greece, NY
  • Hillsboro, OR
  • Chattanooga, TN
  • Ithaca, NY
  • Brooklyn, NY

Work

Position: Executive, Administrative, and Managerial Occupations

Education

Degree: Bachelor's degree or higher

Resumes

Resumes

Peter Vandervoorn Photo 1

Senior Staff Engineer At Intel Corporation

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Position:
Senior Staff Engineer at Intel Corporation
Location:
Portland, Oregon Area
Industry:
Semiconductors
Work:
Intel Corporation since Aug 1998
Senior Staff Engineer
Education:
Cornell University 1992 - 1998
Ph.D, Electrical Engineering Cornell University 1988 - 1992
BS, Electrical Engineering Greece Arcadia High School 1984 - 1988
Peter Vandervoorn Photo 2

Peter Vandervoorn

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Publications

Us Patents

Method For Fabricating A Heterojunction Bipolar Transistor

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US Patent:
20040192002, Sep 30, 2004
Filed:
Mar 31, 2003
Appl. No.:
10/404781
Inventors:
Ravindra Soman - Portland OR, US
Anand Murthy - Portland OR, US
Peter VanDerVoorn - Hillsboro OR, US
Shahriar Ahmed - Portland OR, US
International Classification:
H01L021/8222
US Classification:
438/312000
Abstract:
A bipolar transistor with a SiGe:C film and a seed layer forming beneath the SiGe:C film and methods of making same. The method includes placing a substrate in a reactor chamber and introducing a silicon source gas into the reactor chamber to form a silicon seed layer. The reactor chamber is maintained at a pressure below 45 Torr and a temperature between about 700 C. and 850 C. After the seed layer is formed, the silicon source gas is stopped. The reactor chamber is then simultaneously adjusted to a pressure between about 70 Torr and 90 Torr and a temperature between about 600 C. and 650 C. The silicon source gas, a germanium source gas, and a carbon source gas are introduced to form the SiGe:C film on the seed layer.

Barrier To Amorphization Implant

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US Patent:
20050266654, Dec 1, 2005
Filed:
May 27, 2004
Appl. No.:
10/856283
Inventors:
Michael Hattendorf - Beaverton OR, US
Peter Vandervoorn - Hillsboro OR, US
International Classification:
H01L021/76
US Classification:
438424000
Abstract:
A method includes forming a first and a second semiconductor region which are joined at a semiconductor junction. The first and second semiconductor regions are truncated with an isolation trench, with an end of the semiconductor junction being disposed at the isolation trench. The isolation trench is at least partially filled with an insulation material. A salicide-blocking barrier is formed over a first surface portion of the first semiconductor region proximally disposed relative to the isolation trench. An amorphization implant is implanted in a second surface portion of the first semiconductor region distally disposed relative to the isolation trench. A salicide layer is formed in the amorphization implant.

Tailoring Channel Dopant Profiles

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US Patent:
20060148150, Jul 6, 2006
Filed:
Jan 3, 2005
Appl. No.:
11/028167
Inventors:
Jack Kavalieros - Portland OR, US
Peter Vandervoorn - Hillsboro OR, US
Kelin Kuhn - Aloha OR, US
Justin Brask - Portland OR, US
Mark Doczy - Beaverton OR, US
Matthew Metz - Hillsboro OR, US
Suman Datta - Beaverton OR, US
Robert Chau - Beaverton OR, US
International Classification:
H01L 29/15
H01L 31/0312
H01L 21/336
H01L 21/8234
US Classification:
438197000
Abstract:
Higher mobility transistors may be achieved by removing a dummy metal gate electrode as part of a replacement metal gate process and doping the exposed channel region after source and drains have already been formed. As a result, a retrograde doping profile may be achieved in some embodiments in the channel region which is not adversely affected by subsequent high temperature processing. For example, after already forming the source and drains and thereafter doping the channel, temperature regimes greater than 900 C. may be avoided.

Planar Device On Fin-Based Transistor Architecture

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US Patent:
20160276346, Sep 22, 2016
Filed:
May 27, 2016
Appl. No.:
15/167006
Inventors:
- Santa Clara CA, US
PETER J. VANDERVOORN - Portland OR, US
CHIA-HONG JAN - Portland OR, US
Assignee:
INTEL CORPORATION - Santa Clara CA
International Classification:
H01L 27/088
H01L 29/16
H01L 29/161
H01L 21/8234
Abstract:
Techniques are disclosed for forming a planar-like transistor device on a fin-based field-effect transistor (finFET) architecture during a finFET fabrication process flow. In some embodiments, the planar-like transistor can include, for example, a semiconductor layer which is grown to locally merge/bridge a plurality of adjacent fins of the finFET architecture and subsequently planarized to provide a high-quality planar surface on which the planar-like transistor can be formed. In some instances, the semiconductor merging layer can be a bridged-epi growth, for example, comprising epitaxial silicon. In some embodiments, such a planar-like device may assist, for example, with analog, high-voltage, wide-Z transistor fabrication. Also, provision of such a planar-like device during a finFET flow may allow for the formation of transistor devices, for example, exhibiting lower capacitance, wider Z, and/or fewer high electric field locations for improved high-voltage reliability, which may make such devices favorable for analog design, in some instances.

Precision Resistor For Non-Planar Semiconductor Device Architecture

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US Patent:
20140308785, Oct 16, 2014
Filed:
Jun 24, 2014
Appl. No.:
14/313678
Inventors:
Peter J. Vandervoorn - Hillsboro OR, US
Walid M. Hafez - Portland OR, US
Chia-Hong Jan - Portland OR, US
Curtis Tsai - Beaverton OR, US
Joodong Park - Portland OR, US
International Classification:
H01L 21/8234
H01L 29/66
H01L 49/02
US Classification:
438238
Abstract:
Precision resistors for non-planar semiconductor device architectures are described. In a first example, a semiconductor structure includes first and second semiconductor fins disposed above a substrate. A resistor structure is disposed above the first semiconductor fin but not above the second semiconductor fin. A transistor structure is formed from the second semiconductor fin but not from the first semiconductor fin. In a second example, a semiconductor structure includes first and second semiconductor fins disposed above a substrate. An isolation region is disposed above the substrate, between the first and second semiconductor fins, and at a height less than the first and second semiconductor fins. A resistor structure is disposed above the isolation region but not above the first and second semiconductor fins. First and second transistor structures are formed from the first and second semiconductor fins, respectively.

Planar Device On Fin-Based Transistor Architecture

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US Patent:
20140291766, Oct 2, 2014
Filed:
Mar 30, 2013
Appl. No.:
13/995755
Inventors:
Walid M. Hafez - Portland OR, US
Peter J. Vandervoorn - Portland OR, US
Chia-Hong Jan - Portland OR, US
International Classification:
H01L 27/088
H01L 21/8234
US Classification:
257365, 438296
Abstract:
Techniques are disclosed for forming a planar-like transistor device on a fin-based field-effect transistor (finFET) architecture during a finFET fabrication process flow. In some embodiments, the planar-like transistor can include, for example, a semiconductor layer which is grown to locally merge/bridge a plurality of adjacent fins of the finFET architecture and subsequently planarized to provide a high-quality planar surface on which the planar-like transistor can be formed. In some instances, the semiconductor merging layer can be a bridged-epi growth, for example, comprising epitaxial silicon. In some embodiments, such a planar-like device may assist, for example, with analog, high-voltage, wide-Z transistor fabrication. Also, provision of such a planar-like device during a finFET flow may allow for the formation of transistor devices, for example, exhibiting lower capacitance, wider Z, and/or fewer high electric field locations for improved high-voltage reliability, which may make such devices favorable for analog design, in some instances.

Precision Resistor For Non-Planar Semiconductor Device Architecture

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US Patent:
20140084381, Mar 27, 2014
Filed:
Sep 24, 2012
Appl. No.:
13/625698
Inventors:
Peter J. Vandervoorn - Hillsboro OR, US
Walid M. Hafez - Portland OR, US
Chia-Hong Jan - Portland OR, US
Curtis Tsai - Beaverton OR, US
Joodong Park - Portland OR, US
International Classification:
H01L 27/06
H01L 21/02
US Classification:
257380, 438382, 257E27016, 257E21004
Abstract:
Precision resistors for non-planar semiconductor device architectures are described. In a first example, a semiconductor structure includes first and second semiconductor fins disposed above a substrate. A resistor structure is disposed above the first semiconductor fin but not above the second semiconductor fin. A transistor structure is formed from the second semiconductor fin but not from the first semiconductor fin. In a second example, a semiconductor structure includes first and second semiconductor fins disposed above a substrate. An isolation region is disposed above the substrate, between the first and second semiconductor fins, and at a height less than the first and second semiconductor fins. A resistor structure is disposed above the isolation region but not above the first and second semiconductor fins. First and second transistor structures are formed from the first and second semiconductor fins, respectively.
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Peter C Vandervoorn from Rochester, NY, age ~85 Get Report