Peter A Sandon

6571328, May 27, 2003

Aug 1, 2001

09/919451

Yu-Chung C. Liao - Austin TX
Peter A. Sandon - Essex Junction VT
Howard Cheng - Sammamish WA
Timothy J. Van Hook - Atherton CA

Nintendo Co., Ltd. - Kyoto

G06F 938

712 35, 712 36, 712 22, 712 4

A method and apparatus for obtaining a scalar value from a vector register for use in a mixed vector and scalar instruction, including providing a vector in a vector register file, and embedding a location identifier of the scalar value within the vector in the bits defining the mixed vector and scalar instruction. The scalar value can be used directly from the vector register without the need to load the scalar to a scalar register prior to executing the instruction. The scalar location identifier may be embedded in the secondary op code of the instruction, or the instruction may have dedicated bits for providing the location of the scalar within the vector.

6591361, Jul 8, 2003

Dec 28, 1999

09/473760

Yu-Chung Liao - Austin TX
Peter A. Sandon - Essex Junction VT
Howard Cheng - Redmond WA

International Business Machines Corporation - Armonk NY

G06F 9302

712222, 712221, 708495, 708208, 708517

A method and apparatus that converts integer numbers to/from floating point representations while loading/storing the data. The method and apparatus perform this conversion within a central processing unit having a converter unit and a set of conversion registers. The load/store instructions having data requiring conversion include an index field for identifying one of the conversion registers. Each one of the conversion registers includes information on the type of conversion required and any scaling factors to be applied. Upon receiving one of these instructions, the converter uses the identified conversion register to perform the conversion and stores the converted data into the corresponding register or memory location.

6681296, Jan 20, 2004

Aug 1, 2001

09/918703

Yu-Chung C. Liao - Austin TX
Peter A. Sandon - Essex Junction VT
Howard Cheng - Sammamish WA
Peter Hsu - Fremont CA

Nintendo Co., Ltd. - Kyoto

G06F 1208

711129, 711217, 711214, 711220, 711170, 712 22

A microprocessor including a control unit and a cache connected with the control unit for storing data to be used by the control, wherein the cache is selectively configurable as either a single cache or as a partitioned cache having a locked cache portion and a normal cache portion. The normal cache portion is controlled by a hardware implemented automatic replacement process. The locked cache portion is locked so that the automatic replacement process cannot modify the contents of the locked cache. An instruction is provided in the instruction set that enables software to selectively allocate lines in the locked cache portion to correspond to locations in an external memory, thereby enabling the locked cache portion to be completely managed by software.

6694417, Feb 17, 2004

Apr 10, 2000

09/546025

Yu-Chung Liao - Austin TX
Peter Anthony Sandon - Essex Junction VT

International Business Machines Corporation - Armonk NY

G06F 1202

711170, 711217, 711118, 711145, 710 39

A data processing system may include an interconnect and first and second components coupled to the interconnect for data transfer therebetween. The first component contains a write pipeline that includes an address register and a queue including storage locations for a plurality of data granules. In response to receipt of a plurality of data granules that are each associated with a single address specified by the address register, the queue loads the plurality of data granules into sequential storage locations in order of receipt. Upon the queue being filled with a predetermined number of data granules, the queue outputs, to the second component via the interconnect, the predetermined number of data granules at least two at a time according to the order of receipt. Thus, data transfer efficiency is enhanced while maintaining the relative ordering of the data granules.

6701424, Mar 2, 2004

Apr 7, 2000

09/545183

Yu-Chung C. Liao - Austin TX
Peter A. Sandon - Essex Junction VT
Howard Cheng - Redmond WA

Nintendo Co., Ltd. - Kyoto

G06F 1500

712 35, 712 36, 712 4

A method and apparatus for loading and storing vectors from and to memory, including embedding a location identifier in bits comprising a vector load and store instruction, wherein the location identifier indicates a location in the vector where useful data ends. The vector load instruction further includes a value field that indicates a particular constant for use by the load/store unit to set locations in the vector register beyond the useful data with the constant. By embedding the ending location of the useful date in the instruction, bandwidth and memory are saved by only requiring that the useful data in the vector be loaded and stored.

6794901, Sep 21, 2004

Aug 29, 2002

10/064921

Kerry Bernstein - Underhill VT
Philip G. Emma - Danbury CT
John A. Fifield - Underhill VT
Paul D. Kartschoke - Williston VT
Norman J. Rohrer - Underhill VT
Peter A. Sandon - Essex Junction VT

International Business Machines Corporation - Armonk NY

H03K 19096

326 95, 326 98

An integrated circuit that includes a dynamic logic gate having an output node at which a logical output value of the logic gate is detected and also includes a circuit for selectable alteration of the soft error susceptibility of the dynamic logic gate.

6857061, Feb 15, 2005

Apr 7, 2000

09/545182

Yu-Chung C. Liao - Austin TX, US
Peter A. Sandon - Essex Junction VT, US
Howard Cheng - Sammamish WA, US

Nintendo Co., Ltd. - Kyoto

G08F009/302
G06F007/38

712222, 712213, 712 3, 708501, 708505, 708523

A method and apparatus for obtaining a scalar value from a vector register for use in a mixed vector and scalar instruction, including providing a vector in a vector register file, and embedding a location identifier of the scalar value within the vector in the bits defining the mixed vector and scalar instruction. The scalar value can be used directly from the vector register without the need to load the scalar to a scalar register prior to executing the instruction. The scalar location identifier may be embedded in the secondary op code of the instruction, or the instruction may have dedicated bits for providing the location of the scalar within the vector.

6859862, Feb 22, 2005

Apr 7, 2000

09/545184

Yu-Chung C. Liao - Austin TX, US
Peter A. Sandon - Essex Junction VT, US
Howard Cheng - Redmond WA, US
Peter Hsu - Fremont CA, US

Nintendo Co., Ltd. - Kyoto

G06F012/08

711129, 711130, 711133, 711153, 711152

A microprocessor including a control unit and a cache connected with the control unit for storing data to be used by the control, wherein the cache is selectively configurable as either a single cache or as a partitioned cache having a locked cache portion and a normal cache portion. The normal cache portion is controlled by a hardware implemented automatic replacement process. The locked cache portion is locked so that the automatic replacement process cannot modify the contents of the locked cache. An instruction is provided in the instruction set that enables software to selectively allocate lines in the locked cache portion to correspond to locations in an external memory, thereby enabling the locked cache portion to be completely managed by software.