Resumes
Resumes
Senior Asic Design Engineer
View pageLocation:
7285 west 132Nd St, Overland Park, KS 66213
Industry:
Telecommunications
Work:
Ericsson Aug 2007 - Jan 2013
Senior Asic Design Engineer
Huawei Technologies Aug 2007 - Jan 2013
Senior Asic Design Engineer
Brocade Jul 2006 - Jul 2007
Senior Asic Design Engineer
Tellabs Jul 2004 - Jul 2006
Senior Asic Design Engineer
Cypress Semiconductor Corporation May 2002 - Jul 2004
Senior Asic Design Engineer
Senior Asic Design Engineer
Huawei Technologies Aug 2007 - Jan 2013
Senior Asic Design Engineer
Brocade Jul 2006 - Jul 2007
Senior Asic Design Engineer
Tellabs Jul 2004 - Jul 2006
Senior Asic Design Engineer
Cypress Semiconductor Corporation May 2002 - Jul 2004
Senior Asic Design Engineer
Education:
University of California, Berkeley 1995 - 1997
Technische Universität Wien 1985 - 1988
Masters, Master of Science In Electrical Engineering, Engineering Technische Universität Wien 1983 - 1985
Bachelors, Bachelor of Science In Electrical Engineering, Electrical Engineering
Technische Universität Wien 1985 - 1988
Masters, Master of Science In Electrical Engineering, Engineering Technische Universität Wien 1983 - 1985
Bachelors, Bachelor of Science In Electrical Engineering, Electrical Engineering
Skills:
Asic
Verilog
Systemverilog
Perl
Fpga
Formal Verification
Unix
Hardware Architecture
Algorithms
Tcp/Ip
Debugging
Simulations
System Verilog
Jasper
Cvs
Awk
Perforce
Visio
Tcam
Interlaken
Sed
Windows
Grep
Verilog
Systemverilog
Perl
Fpga
Formal Verification
Unix
Hardware Architecture
Algorithms
Tcp/Ip
Debugging
Simulations
System Verilog
Jasper
Cvs
Awk
Perforce
Visio
Tcam
Interlaken
Sed
Windows
Grep
Languages:
German
English
Spanish
English
Spanish