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Peter R Kinget

from Summit, NJ
Age ~57
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Related to:
Nicholas KingetAndreas P Kinget, 26Andreas KingetDenabeele VanInge Kinget, 56
Connected to:
Leslie J Kingeter, 65Mike K Kingfisher, 83Kim Kinggard, 45George T Kingham, 83Randall E Kingham, 71Adam G Kinghorn, 36Anne M Kinghorn, 67April S Kinghorn, 43Christina E Kinghorn, 49Harry Kinghorn, 116

Peter Kinget Phones & Addresses

  • 11 Franklin Pl, Summit, NJ 07901 (908) 522-0011
  • Aliso Viejo, CA
  • Hoboken, NJ
  • 150 Morris Ave, Springfield, NJ 07081
  • 11 Franklin Pl, Summit, NJ 07901 (908) 472-3894

Work

Company: Seamless devices Nov 2014 to Oct 2017 Position: Technical advisor

Education

Degree: Doctorates, Doctor of Philosophy School / High School: Ku Leuven Faculty of Engineering Technology & Faculty of Movement and Rehabilitation Sciences Sep 1991 to Jun 1996 Specialities: Electrical Engineering

Skills

Cmos • Ic • Analog • Integrated Circuit Design • Rf • Vlsi • Analog Circuit Design • Wireless • Electrical Engineering • Simulations • Semiconductors • Circuit Design • Power Management • Mixed Signal • Bicmos • Matlab • Characterization • R&D • Asic • Research • Microelectronics • Wireless Communications Systems • Analog Signal Processing • Rf Engineering • Rf Design • Radio Frequency Engineering • Mixed Signal Ic Design • Analog Filters • Transistors • Computer Architecture • Hardware Architecture • Pspice • Integrated Circuits • Radio Frequency • Very Large Scale Integration • Expert Witness • Adcs • Simulink • Digital Signal Processing • Numerical Analysis

Languages

English • Dutch • French

Industries

Semiconductors

Resumes

Resumes

Peter Kinget Photo 1

Consulting And Testifying Expert In Patent Litigation

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Location:
16215 Alton Pkwy, Irvine, CA 92618
Industry:
Semiconductors
Work:
Seamless Devices Nov 2014 - Oct 2017
Technical Advisor
Columbia University In the City of New York Nov 2014 - Oct 2017
Chair of Department of Electrical Engineering
Various Major Ip Law Firms Nov 2014 - Oct 2017
Consulting and Testifying Expert In Patent Litigation
Columbia University In the City of New York Nov 2014 - Oct 2017
Bernard J Lechner Professor of Electrical Engineering
Celight Aug 2000 - Jan 2002
Director, Vlsi Design
Education:
Ku Leuven Faculty of Engineering Technology & Faculty of Movement and Rehabilitation Sciences Sep 1991 - Jun 1996
Doctorates, Doctor of Philosophy, Electrical Engineering Ku Leuven Faculty of Engineering Technology & Faculty of Movement and Rehabilitation Sciences Sep 1985 - Jul 1990
Skills:
Cmos
Ic
Analog
Integrated Circuit Design
Rf
Vlsi
Analog Circuit Design
Wireless
Electrical Engineering
Simulations
Semiconductors
Circuit Design
Power Management
Mixed Signal
Bicmos
Matlab
Characterization
R&D
Asic
Research
Microelectronics
Wireless Communications Systems
Analog Signal Processing
Rf Engineering
Rf Design
Radio Frequency Engineering
Mixed Signal Ic Design
Analog Filters
Transistors
Computer Architecture
Hardware Architecture
Pspice
Integrated Circuits
Radio Frequency
Very Large Scale Integration
Expert Witness
Adcs
Simulink
Digital Signal Processing
Numerical Analysis
Languages:
English
Dutch
French

Business Records

Name / Title
Company / Classification
Phones & Addresses
Peter Kinget
Mbr
Regis Ic Labs Limited Liability Company
Business Consulting Services
11 Franklin Pl, Summit, NJ 07901
(908) 294-6456

Publications

Isbn (Books And Publications)

Analog Circuit Design Techniques At 0. 5V

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Author

Peter Kinget

ISBN #

0387699538

Analog Vlsi Integration of Massive Parallel Processing Systems

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Author

Peter Kinget

ISBN #

0792398238

Us Patents

Glitch-Free Phase Switching Synthesizer

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US Patent:
6671341, Dec 30, 2003
Filed:
Sep 17, 1999
Appl. No.:
09/398371
Inventors:
Peter Kinget - Aliso Viejo CA
Nagendra Krishnapura - New York NY
Assignee:
Agere Systems, Inc. - Berkeley Heights NJ
International Classification:
H03D 324
US Classification:
375373, 375376
Abstract:
A system for generating a glitch-free output signal having a frequency. The system comprises a frequency divider for receiving a signal having an input frequency, wherein the frequency divider is configured to generate a plurality of corresponding phase-shifted signals. A retimer is coupled to the frequency divider and is configured to receive the phase-shifted signals and to generate multiplexer input signals for receipt by a multiplexer. The retimer is further configured to receive retimer control signals and to generate corresponding multiplexer control signals. The multiplexer is coupled to the retimer and has input terminals configured to receive the multiplexer input signals. The multiplexer is controlled by the multiplexer control signals so as to alternately and successively provide at its output terminal one of the multiplexer input signals. As the signal level of each phase-shifted signal transitions between a âhighâ position and a âlowâ position, the multiplexer control signals are configured to be employed at a time corresponding to the time when a phase-shifted signal experiences a transition.

System And Method For Orthogonal Frequency Division Multiplexed Optical Communication

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US Patent:
7076169, Jul 11, 2006
Filed:
Feb 28, 2002
Appl. No.:
10/087022
Inventors:
Isaac Shpantzer - Bethesda MD, US
Yehouda Meiman - Rishon Letzion, IL
Michael Tseytlin - Bethesda MD, US
Olga Ritterbush - Rockville MD, US
Aviv Salamon - Washington DC, US
Peter Feldman - Short Hills NJ, US
Alper Demir - Istanbul, TR
Peter Kinget - Summit NJ, US
Nagendra Krishnapura - Hoboken NJ, US
Jaijeet Roychowdhury - Minneapolis MN, US
Assignee:
CeLight, Inc. - Silver Spring MD
International Classification:
H04J 14/06
H04J 4/00
H04B 10/00
H04B 10/04
H04B 10/06
US Classification:
398 76, 398 65, 398 74, 398152, 398163, 398184, 398185, 398205
Abstract:
A system for optical communication send optical signals over a plurality of wavelength channels. Each wavelength channel comprises a number of orthogonal subchannel frequencies which are spaced apart from one another by a predetermined amount. Each of the subchannel frequencies is modulated with data from a data stream. The data modulation scheme splits a subchannel frequency code into H and V components, and further processes the components prior to modulation with data. The various data-modulated subchannels are then combined into a single channel for transmission. The received signals are detected and demodulated with the help of a symbol timing recovery module which establishes the beginning and end of each symbol. A polarization mode distortion compensation module at the receiver is used to mitigate the effects to polarization more distortion in the fiber.

Digital If Demodulator For Video Applications

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US Patent:
7106388, Sep 12, 2006
Filed:
Dec 15, 2000
Appl. No.:
09/739349
Inventors:
Pieter Vorenkamp - Laguna Niguel CA, US
Myles H. Wakayama - Laguna Niguel CA, US
Steven Jaffe - Irvine CA, US
Frank Carr - Dove Canyon CA, US
Arnoldus Venes - Laguna Niguel CA, US
Peter R. Kinget - Summit NJ, US
Daniel J. Marz - San Diego CA, US
Thinh Nguyen - San Jose CA, US
Assignee:
Broadcom Corporation - Irvine CA
International Classification:
H04N 5/455
US Classification:
348726, 348725, 348731, 348735
Abstract:
An integrated communications system. A substrate having a receiver disposed on the substrate for converting a received signal to an IF signal, a digital IF demodulator disposed on the substrate and coupled to the receiver for converting the IF signal to a demodulated baseband signal, and a transmitter disposed on the substrate operating in cooperation with the receiver to establish a two way communications path.

System And Method For Code Division Multiplexed Optical Communication

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US Patent:
7167651, Jan 23, 2007
Filed:
Sep 26, 2001
Appl. No.:
09/962243
Inventors:
Isaac Shpantzer - Bethesda MD, US
Michael Tseytlin - Bethesda MD, US
Yaakov Achiam - Rockville MD, US
Aviv Salamon - Washington DC, US
Israel Smilanski - Rockville MD, US
Olga Ritterbush - Rockville MD, US
Pak Shing Cho - Gaithersburg MD, US
Li Guoliang - North Potomac MD, US
Jacob Khurgin - Baltimore MD, US
Yehouda Meiman - Rishon Letzion, IL
Alper Demir - Jersey City NJ, US
Peter Feldman - Short Hills NJ, US
Peter Kinget - Summit NJ, US
Nagendra Krishnapura - Hoboken NJ, US
Jaijeet Roychowdhury - Minneapolis MN, US
Joseph Schwarzwalder - Gaithersburg MD, US
Charles Sciabarra - Ellicott City MD, US
Assignee:
CeLight, Inc. - Silver Spring MD
International Classification:
H04J 4/00
H04B 10/00
H04B 10/04
H04B 10/06
US Classification:
398 77, 398 74, 398152, 398184, 398205
Abstract:
A system for optical communication forms a family of orthogonal optical codes modulated by a data stream. The orthogonal codes are formed by creating a stream of evenly spaced-apart pulses using a pulse spreader circuit and modulating the pulses in amplitude and/or phase to form a family of orthogonal optical code words, each representing a symbol. A spreader calibration circuit is used to ensure accurate timing and modulation. Each code word is further modulated by a predetermined number of data bits. The data modulation scheme splits a code word into H and V components, and further processes the components prior to modulation with data, followed by recombining with a polarization beam combiner. The data-modulated code word is then sent, along with others to receiver. The received signal is detected and demodulated with the help of a symbol synchronization unit which establishes the beginning and end of the code words.

Low Voltage Operational Transconductance Amplifier Circuits

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US Patent:
7847633, Dec 7, 2010
Filed:
Sep 20, 2005
Appl. No.:
11/663377
Inventors:
Peter R. Kinget - Summit NJ, US
Assignee:
The Trustees of Columbia University in the City of New York - New York NY
International Classification:
H03F 3/45
US Classification:
330253, 330258
Abstract:
Circuits that operate with power supplies of less than 1 volt are presented. More particularly, circuits that operate with supply voltages (VDD) near or lower than the threshold voltage of the transistors (, etc. ) in those circuits are presented. Various circuits and embodiments such as operational transconductance amplifiers (), biasing circuits, integrators, continuous-time sigma delta modulators, track-and-hold circuits, and others are presented. The techniques and circuits can be used in a wide range of applications and various transistors from metal-oxide-semiconductor to bipolar junction transistors may implement the techniques presented herein.

Systems And Methods For Reducing Circuit Area

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US Patent:
7847667, Dec 7, 2010
Filed:
Nov 20, 2007
Appl. No.:
11/943287
Inventors:
Peter R. Kinget - Summit NJ, US
Frank Zhang - Edison NJ, US
Assignee:
The Trustees of Columbia University in the City of New York - New York NY
International Classification:
H01F 5/00
US Classification:
336200
Abstract:
Methods and systems are provided for reducing circuit area. Some embodiments provide electronic devices including an inductor formed from a path having two ends that loops substantially in a plane around a center area, wherein the path crosses itself at least two points and wherein the path defines an outer boundary of the inductor; and a circuit that is located within the outer boundary of the inductor and substantially within or adjacent to the plane. Other embodiments provide electronic devices including an inductor formed from a path having two ends that loops substantially in a plane around a center area, wherein the path defines an outer boundary of the inductor; and a circuit that is located within the outer boundary of the inductor and substantially within or adjacent to the plane, and wherein the circuit comprises a signal path that is rake-shaped and crosses the path of the inductor at substantially perpendicular angles.

Circuits For Forming The Inputs Of A Latch

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US Patent:
7884658, Feb 8, 2011
Filed:
Mar 31, 2008
Appl. No.:
12/060190
Inventors:
Peter Kinget - Summit NJ, US
Shih-an Yu - New York NY, US
Assignee:
The Trustees of Columbia University in the City of New York - New York NY
International Classification:
H03K 3/356
US Classification:
327208, 327218, 326112
Abstract:
Circuits for forming the inputs of a latch are provided. In some embodiments, circuits for forming inputs of a latch comprise: a first transistor having a first gate terminal, a first drain terminal, a first source terminal, a first gate length, and a first common mode level at the first gate terminal, wherein the first gate terminal provides a data input to the latch; and a second transistor having a second gate terminal, a second drain terminal, a second source terminal, a second gate length, and a second common mode level at the second gate terminal, wherein the second gate terminal provides a clock input to the latch, the second drain terminal is coupled to the first source terminal, and the first gate length and the second gate length are sized so that the first common model level and the second common mode level are substantially equal.

Low Voltage Operational Transconductance Amplifier Circuits

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US Patent:
8030999, Oct 4, 2011
Filed:
Sep 20, 2005
Appl. No.:
11/663376
Inventors:
Shouri Chatterjee - New Delhi, IN
Peter R. Kinget - Summit NJ, US
Yannis Tsividis - New York NY, US
Assignee:
The Trustees of Columbia University in the City of New York - New York NY
International Classification:
H03F 3/45
US Classification:
330253, 330258
Abstract:
Circuits (FIG. ) that operate with power supplies (VDD) of less than 1 Volt are present. More particularly, circuits (FIG. ) that operate with supply voltages (VDD) near or lower than the threshold voltage of the transistors (MA, MB) in those circuits are presented. Various circuits and embodiments such as operational transconductance amplifiers, biasing circuits, integrators, continuous-time sigma delta modulators, track-and-hold circuits, and others are presented. The techniques and circuits can be used in a wide range of applications and various transistors from metal-oxide-semiconductor (MOS) to bipolar junction transistors may implement the techniques presented herein.
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Peter R Kinget from Summit, NJ, age ~57 Get Report