Peter Dice Phones & Addresses
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Folsom, CA
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Chandler, AZ
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Cameron Park, CA
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8842 Winding Way, Fair Oaks, CA 95628 (916) 965-6264
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Maricopa, AZ
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Claryville, NY
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East Windsor, NJ
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3426 Oxford Rd, Cameron Park, CA 95682
Work
Position:
Building and Grounds Cleaning and Maintenance Occupations
Education
Degree:
High school graduate or higher
Publications
Us Patents
Mechanism For Facilitating Faster Suspend/Resume Operations In Computing Systems
View pageUS Patent:
20140068302, Mar 6, 2014
Filed:
Aug 28, 2012
Appl. No.:
13/596915
Inventors:
Ohad Falik - Kfar Saba, IL
Eliezer Weissmann - Haifa, IL
Alon Naveh - Ramat Hasharon, IL
Michael Mishaeli - Zichron Yaakov, IL
Nadav Shulman - Tel Mond, IL
Robert E. Gough - Sherwood OR, US
Erik C. Bjorge - Hillsboro OR, US
Douglas R. Moran - Folsom CA, US
Peter A. Dice - Chandler AZ, US
Eliezer Weissmann - Haifa, IL
Alon Naveh - Ramat Hasharon, IL
Michael Mishaeli - Zichron Yaakov, IL
Nadav Shulman - Tel Mond, IL
Robert E. Gough - Sherwood OR, US
Erik C. Bjorge - Hillsboro OR, US
Douglas R. Moran - Folsom CA, US
Peter A. Dice - Chandler AZ, US
International Classification:
G06F 1/32
US Classification:
713323
Abstract:
A mechanism is described for facilitating faster suspend/resume operations in computing systems according to one embodiment of the invention. A method of embodiments of the invention includes initiating an entrance process into a first sleep state in response to a sleep call at a computing system, transforming from the first sleep state to a second sleep state. The transforming may include preserving at least a portion of processor context at a local memory associated with one or more processor cores of a processor at the computing system. The method may further include entering the second sleep state.
Providing A Trusted Execution Environment Using A Processor
View pageUS Patent:
20170140153, May 18, 2017
Filed:
Feb 1, 2017
Appl. No.:
15/421539
Inventors:
- Santa Clara CA, US
Peter J. Barry - Arndcrusha, IE
Rajesh Poornachandran - Portland OR, US
Arjan Van De Ven - Portland OR, US
Peter A. Dice - Chandler AZ, US
Gopinatth Selvaraje - Portland OR, US
Julien Carreno - Ennis, IE
Lee G. Rosenbaum - Hillsboro OR, US
Peter J. Barry - Arndcrusha, IE
Rajesh Poornachandran - Portland OR, US
Arjan Van De Ven - Portland OR, US
Peter A. Dice - Chandler AZ, US
Gopinatth Selvaraje - Portland OR, US
Julien Carreno - Ennis, IE
Lee G. Rosenbaum - Hillsboro OR, US
International Classification:
G06F 21/57
G06F 9/44
H04L 9/30
G06F 21/53
H04L 9/08
H04L 9/14
G06F 9/44
H04L 9/30
G06F 21/53
H04L 9/08
H04L 9/14
Abstract:
In an embodiment, a system on a chip includes: a single core to execute a legacy instruction set, the single core configured to enter a system management mode (SMM) to provide a trusted execution environment to perform at least one secure operation; and a memory controller coupled to the single core, the memory controller to interface with a system memory, where a portion of the system memory comprises a secure memory for the SMM, and the single core is to authenticate and execute a boot firmware, and pass control to the SMM to obtain a key pair from a protected storage and store the key pair in the secure memory. Other embodiments are described and claimed.
Providing A Trusted Execution Environment Using A Processor
View pageUS Patent:
20160070932, Mar 10, 2016
Filed:
Sep 10, 2014
Appl. No.:
14/482136
Inventors:
Vincent J. Zimmer - Federal Way WA, US
Peter J. Barry - Arndcrusha, IE
Rajesh Poornachandran - Portland OR, US
Arjan Van De Ven - Portland OR, US
Peter A. Dice - Chandler AZ, US
Gopinatth Selvaraje - Portland OR, US
Julien Carreno - Ennis, IE
Lee G. Rosenbaum - Hillsboro OR, US
Peter J. Barry - Arndcrusha, IE
Rajesh Poornachandran - Portland OR, US
Arjan Van De Ven - Portland OR, US
Peter A. Dice - Chandler AZ, US
Gopinatth Selvaraje - Portland OR, US
Julien Carreno - Ennis, IE
Lee G. Rosenbaum - Hillsboro OR, US
International Classification:
G06F 21/72
G06F 21/79
G06F 21/57
H04L 9/08
G06F 21/79
G06F 21/57
H04L 9/08
Abstract:
In an embodiment, a system on a chip includes: a single core to execute a legacy instruction set, the single core configured to enter a system management mode (SMM) to provide a trusted execution environment to perform at least one secure operation; and a memory controller coupled to the single core, the memory controller to interface with a system memory, where a portion of the system memory comprises a secure memory for the SMM, and the single core is to authenticate and execute a boot firmware, and pass control to the SMM to obtain a key pair from a protected storage and store the key pair in the secure memory. Other embodiments are described and claimed.