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Pei-Ming D Chow

from Los Angeles, CA
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Also known as:
Feiming D Chow, Pei Ming Chow, Peiming D Chow
Related to:
Steve Liu, 65Eric H Liu, 61Connie Chow, 35Jennie Y Liu, 51Hai Sanliao, 67Pei Ming Dchow, 71Timothy Bowen Chow, 32
Connected to:
Adam L Chow, 47Alicia K Chow, 55Alison C Chow, 38Alissa L Chow, 53Alton T Chow, 69Alvin W Chow, 57Amen Y Chow, 60Anthony Chow, 58Antony W Chow, 56April Chow, 31

Pei-Ming Chow Phones & Addresses

  • Los Angeles, CA
  • Santa Monica, CA

Publications

Us Patents

Adaptive-Biased Mixer

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US Patent:
7356317, Apr 8, 2008
Filed:
Jul 14, 2004
Appl. No.:
10/890712
Inventors:
Zhiwei Xu - Los Angeles CA, US
Pei-Ming Daniel Chow - Los Angeles CA, US
M. Frank Chang - Los Angeles CA, US
Assignee:
Silicon Storage Technology, Inc. - Sunnyvale CA
International Classification:
H04B 1/10
H04B 1/26
US Classification:
455130, 455305, 455326, 330259
Abstract:
A system or method for a circuit network that receives an RF signal, and where a plurality of switching transistors receive an RF signal output by the circuit network and perform mixing with a local oscillation (LO) signal received on a LO input. An active bias circuit performs active bias of the plurality of switching transistors in a feedback loop provided between the LO input and an output of the plurality of switching transistors.

Integrated Power Detector With Temperature Compensation For Fully-Closed Loop Control

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US Patent:
7852063, Dec 14, 2010
Filed:
Jun 4, 2008
Appl. No.:
12/133297
Inventors:
Bun Kobayashi - Cypress CA, US
Liyang Zhang - West Hills CA, US
Pei-Ming Daniel Chow - Los Angeles CA, US
Assignee:
Silicon Storage Technology, Inc. - Sunnyvale CA
International Classification:
G01R 5/22
US Classification:
324105
Abstract:
An amplifier circuit comprises a detection power input circuit for receiving an RF signal, and a bias circuit that includes an output for generating a bias signal in response to a reference control voltage. The power detector further comprises a detection circuit for generating a power control voltage having a voltage characteristic that offsets temperature characteristics of the received RF signal. The amplifier circuit further comprises a power amplifier coupled to the bias circuit. The power amplifier includes a driver stage providing the RF signal. The detection circuit compensates temperature variation of the inputted detection voltage of the received RF signal.

Integrated Power Detector With Temperature Compensation For Fully-Closed Loop Control

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US Patent:
7893684, Feb 22, 2011
Filed:
Aug 2, 2010
Appl. No.:
12/848937
Inventors:
Bun Kobayashi - Cypress CA, US
Liyang Zhang - West Hills CA, US
Pei-Ming Daniel Chow - Los Angeles CA, US
Assignee:
Silicon Storage Technology, Inc. - Sunnyvale CA
International Classification:
G01R 5/22
US Classification:
324105
Abstract:
An amplifier circuit comprises a detection power input circuit for receiving an RF signal, and a bias circuit that includes an output for generating a bias signal in response to a reference control voltage. The power detector further comprises a detection circuit for generating a power control voltage having a voltage characteristic that offsets temperature characteristics of the received RF signal. The amplifier circuit further comprises a power amplifier coupled to the bias circuit. The power amplifier includes a driver stage providing the RF signal. The detection circuit compensates temperature variation of the inputted detection voltage of the received RF signal.

Attenuator With A Control Circuit

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US Patent:
7965152, Jun 21, 2011
Filed:
Dec 2, 2008
Appl. No.:
12/326791
Inventors:
Bun Kobayashi - Cypress CA, US
Steven W. Schell - Torrance CA, US
Pei-Ming Daniel Chow - Los Angeles CA, US
Assignee:
Microchip Technology Incorporated - Chandler AZ
International Classification:
H01P 1/22
US Classification:
333 81R, 327308
Abstract:
An attenuator system comprises an attenuator and a control circuit for controlling the attenuation of the attenuator. In one embodiment, the attenuator comprises two diodes or two diode connected transistors, and the control circuit comprises two transistors as the only active devices. In another embodiment, the control circuit comprises another transistor in a shut down circuit.

Amplifier Circuit With Step Gain

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US Patent:
8115552, Feb 14, 2012
Filed:
Jan 11, 2010
Appl. No.:
12/685635
Inventors:
Bun Kobayashi - Cypress CA, US
Steven W. Schell - Torrance CA, US
Yonghan Chris Kim - La Mirada CA, US
Pei-Ming Daniel Chow - Los Angeles CA, US
Assignee:
Microchip Technology Incorporated - Chandler AZ
International Classification:
H03G 3/30
US Classification:
330281, 330285
Abstract:
A step gain amplifier has an amplifier with an input and an output, and a bias circuit connected to the input and to a bias node. A passive feedback circuit using only passive elements connects the output to the input. A control circuit is connected to the bias circuit at the bias node.

Digital Control Interface In Heterogeneous Multi-Chip Module

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US Patent:
8264272, Sep 11, 2012
Filed:
Apr 22, 2009
Appl. No.:
12/428362
Inventors:
Liyang Zhang - West Hills CA, US
Pei-Ming Daniel Chow - Los Angeles CA, US
Assignee:
Microchip Technology Incorporated - Chandler AZ
International Classification:
H03K 19/0175
H03F 3/04
H03F 3/20
US Classification:
327433, 327333, 327566, 326 64, 326 84, 330157
Abstract:
A front-end module comprises a plurality of chips that includes first and second functional blocks and an interconnection circuit. The first functional block is formed using a first process type and includes a digital control circuit that generates a digital control signal in response to an external control signal from outside the front end module. The second functional block is formed using a second process type and includes a digitally controlled circuit controlled by the digital control signal generated by the first functional block. The second process type is different from the first process type. The interconnection circuit couples the digital control circuit and the digitally controlled circuit to provide the digital control signal to the digitally controlled circuit. In one aspect, the first functional block may be a low noise amplifier formed by a pseudomorphic high electron mobility transistor process. The second functional block may be a power amplifier formed by a heterojunction bipolar transistor process.

Focal Plane Imaging Array With Internal Calibration Source

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US Patent:
54383366, Aug 1, 1995
Filed:
Nov 12, 1993
Appl. No.:
8/151713
Inventors:
Paul S. C. Lee - La Palma CA
Pei-Ming D. Chow - Los Angeles CA
John J. Berenz - San Pedro CA
Jay S. Pearlman - Rancho Palos Verdes CA
Wayne W. Lam - Manhattan Beach CA
Assignee:
TRW Inc. - Redondo Beach CA
International Classification:
G01S 740
US Classification:
342174
Abstract:
A focal plane imaging array (FPIA) (16) for use in a direct detection imaging device (10) for conducting radiometric imaging at microwave and millimeter-wave frequencies is disclosed as having an internal electronic calibration source (36). The plurality of energy detecting pixel elements (14) which comprise the FPIA (16) include a detection circuit (34) and a calibration circuit (36). The calibration circuit (36) is uni-directionally coupled to the detection circuit (34) to allow a known calibration signal "pulse" to be introduced into the detection circuit (34). The calibration pulse is processed by the pixel detection circuit and the output signal is compared with the pixel's responsivity value. Adjustments in the pixel gain and sensitivity may then be made as appropriate.

Mask Alignment Measurement Structure For Semiconductor Fabrication

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US Patent:
45715386, Feb 18, 1986
Filed:
Apr 25, 1983
Appl. No.:
6/488225
Inventors:
Pei-Ming D. Chow - Redondo Beach CA
Assignee:
Rockwell International Corporation - El Segundo CA
International Classification:
H01L 2166
G01R 2702
US Classification:
324 65R
Abstract:
A method of quantitatively measuring the relative alignment of elements on a surface of a semiconductor body formed by two sequential masking steps during processing is provided. A fixed pattern of rectangular images are formed on a first mask; and a fixed pattern of repeating U-shaped images are formed on a second mask. The semiconductor body is processed so that the rectangular images on the first mask align with the U-shaped images on the second mask. An electrical probe is applied to opposed ends of the boustrophederal pattern formed and the electrical resistance measured to determine a parameter related to the relative alignment of elements on the semiconductor body.
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Pei-Ming D Chow from Los Angeles, CA Get Report