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Pei Hsing Luo

from Austin, TX
Age ~57
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Also known as:
Pei H Luo, Pei H Wang, Peihsin Luo, Hsing Luo Peu, Luo Hsing, Pei Hsing I, G Luo, Hsing Luo G
Related to:
Helen H Burrows, 43
Connected to:
Anna S Luo, 61Audrey Luo, 29Billy G Luo, 72Bin Luo, 67Brince Luo, 77Christina M Luo, 55Chuanjiang Luo, 42Claudia H Luo, 56Congyun C Luo, 63Dengpan Luo, 54

Pei Luo Phones & Addresses

  • Austin, TX
  • Frisco, TX
  • Plano, TX
  • Irvine, CA
  • Fremont, CA
  • Hacienda Heights, CA
  • Naperville, IL
  • Downers Grove, IL
  • La Puente, CA
  • Chicago, IL

Resumes

Resumes

Pei Luo Photo 1

Pei Luo

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Pei Luo Photo 2

Pei Luo

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Pei Luo Photo 3

Analyst

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Position:
Analyst at T. H. Advisors
Location:
New York, New York
Industry:
Financial Services
Work:
T. H. Advisors since Jan 2011
Analyst
Citibank Jun 2008 - Jul 2008
Summer Intern
Education:
Washington University in St. Louis 2009 - 2010
Master of Science in Finance, Finance Washington University in St. Louis - Olin Business School 2009 - 2010
Zhejiang University 2005 - 2009
BA, Finance and Economics
Pei Luo Photo 4

Pei Luo

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Business Records

Name / Title
Company / Classification
Phones & Addresses
Pei Ru Luo
President
MAX & KAREN INT'L TRADING INC
1405 Stevens Ave #6, San Gabriel, CA 91776

Publications

Us Patents

Enhanced Scalar Vector Dual Pipeline Architecture With Cross Execution

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US Patent:
20200264879, Aug 20, 2020
Filed:
Feb 20, 2019
Appl. No.:
16/281054
Inventors:
- Nanjing, CN
Pingping Shao - San Jose CA, US
Pei Luo - San Jose CA, US
Assignee:
Nanjing Iluvatar CoreX Technology Co., Ltd. (DBA "Iluvatar CoreX Inc. Nanjing") - Nanjing
International Classification:
G06F 9/30
G06F 9/38
G06F 9/48
G06F 15/80
Abstract:
Embodiments of the invention may provide a technical solution by identifying a set of scalar and vector instructions. The set of scalar and vector instructions may be set to be executed in a kernel. A scalar instruction of the set of scalar and vector instructions is compared to a predefined set of scalar instructions. Based on the comparison, a secondary scalar pipeline is generated for the scalar instruction for processing. The remaining scalar instructions from the set of scalar and vector instructions is assigned to a first scalar pipeline. Vector instructions of the set of scalar and vector instructions are assigned to a vector pipeline.

Constant Scalar Register Architecture For Acceleration Of Delay Sensitive Algorithm

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US Patent:
20200264891, Aug 20, 2020
Filed:
Feb 20, 2019
Appl. No.:
16/281052
Inventors:
- Nanjing, CN
Pingping Shao - San Jose CA, US
Pei Luo - San Jose CA, US
Assignee:
Nanjing Iluvatar CoreX Technology Co., Ltd. (DBA “Iluvatar CoreX Inc. Nanjing”) - Nanjing
International Classification:
G06F 9/38
G06F 9/30
Abstract:
Embodiments of the invention provides a technical solution by modifying or changing unused scalar register to become constant scalar register. By using unused scalar register, aspects of the invention may decrease latency of scalar processing while decrease reiteration in the scalar processing. Embodiments of the invention further reduce the need for separate data store units, such as cache or other storage units.

Method For Physical Layer Security Protection Using Public Keys

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US Patent:
20190149986, May 16, 2019
Filed:
Jan 10, 2019
Appl. No.:
16/245009
Inventors:
Pei Luo - Carrollton TX, US
Ellen Liao - Hillsboro OR, US
Lu Lu - Hillsboro OR, US
Joonbeom Kim - Carrollton TX, US
International Classification:
H04W 12/04
H04W 12/00
H04W 72/04
H04W 76/27
H04W 8/22
H04L 9/08
H04L 1/00
Abstract:
Embodiments of a User Equipment (UE), Next Generation Node-B (gNB) and methods of communication are generally described herein. The UE may randomly select a private key of the UE. The UE may receive, from the gNB, control signaling that includes a public key of the gNB. The UE may generate a shuffling key based at least partly on a public function of the private key of the UE and the public key of the gNB. The UE may determine a random sequence of bits based on a random number generation operation with the shuffling key as a seed. The UE may determine, based on the random sequence of bits, a shuffling array for shuffling of coded bits. The UE may generate the coded bits, and may shuffle the coded bits in accordance with the shuffling array.
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Pei Hsing Luo from Austin, TX, age ~57 Get Report