US Patent:
20190257882, Aug 22, 2019
Inventors:
- Ogden UT, US
Jayson Kelly - Roy UT, US
Brent Sorensen - Roy UT, US
Paul Sorensen - Roy UT, US
International Classification:
G01R 31/3185
G06F 11/22
G05B 19/042
G05B 23/02
Abstract:
Embodiments are directed to identifying intermittent faults in a unit under test (UUT), and to mapping interconnections between connection points in a UUT. In one scenario, a testing apparatus includes an interface for electrically attaching the UUT to a testing module and an input circuit for supplying an individual stimulus signal to each unpowered connection point in the UUT. The testing apparatus also includes an active intermittence detecting circuit electronically connected to each connecting point in the UUT. A stimulus signal is applied simultaneously to each connecting line, so that an intermittent fault on any line will generate a trigger on those connection lines that have an intermittent fault. The testing apparatus also includes a logic circuit that determines when a trigger has been generated on the UUT, determines the connection point of the trigger, assigns a timestamp to the intermittent fault, and generates reporting data for the intermittent fault.
