US Patent:
20220230700, Jul 21, 2022
Inventors:
- Boise ID, US
Michael R. Spica - Eagle ID, US
Donald Shepard - Longmont CO, US
Patrick Caraher - Longmont CO, US
João Elmiro da Rocha Chaves - Middleton ID, US
International Classification:
G11C 29/44
G11C 29/56
G11C 29/36
G06F 9/50
G11C 29/22
Abstract:
A detection is made by a processing device allocated to a memory device test board of a distributed test platform that a memory sub-system has engaged with a memory device test resource of the memory device test board. A test is identified to be performed for a memory device of the memory sub-system. The test includes first instructions to be executed by a memory sub-system controller of the memory sub-system in performance of the test and second instructions to be executed by the processing device in performance of the test. The second instructions are to cause one or more test condition components of the memory device test resource to generate one or more test conditions to be applied to the memory device while the memory sub-system executes the first instructions. Responsive to a transmission of the first instructions to the memory sub-system controller, the second instructions are executed.