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Norman Te Godinho

from Los Altos Hills, CA
Age ~84

Norman Godinho Phones & Addresses

  • 12250 Menalto Dr, Los Altos Hills, CA 94022
  • 27872 Via Corita Way, Los Altos, CA 94022
  • Mountain View, CA

Publications

Us Patents

High Resistance Polysilicon Load Resistor

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US Patent:
51722119, Dec 15, 1992
Filed:
Jan 12, 1990
Appl. No.:
7/464094
Inventors:
Norman Godinho - Los Altos Hills CA
Frank T. W. Lee - Monte Sereno CA
Richard F. Motta - Los Altos CA
Joseph Tzou - Belmont CA
Jai-man Balk - San Jose CA
Assignee:
Paradigm Technology, Inc. - San Jose CA
International Classification:
H01L 2702
H01L 2348
H01L 2946
US Classification:
257536
Abstract:
A load resistor for use in a semiconductor integrated circuit consists of two portions of conductive material, typically strips of either a silicide or a composite polycrystalline silicon layer and silicide layer formed thereon, formed on a semiconductor substrate and separated from each other by a selected distance. An electrically conductive dopant diffusion barrier is formed on the first and second portions of conductive material. A polycrystalline silicon material is then placed on the structure such that one portion of the polycrystalline silicon material is in ohmic contact through the diffusion barrier with the first portion of conductive material and the other portion of the polycrystalline silicon material is in ohmic contact through the diffusion barrier with the second portion of conductive material. Typically the polycrystalline silicon material is placed on an insulation layer formed on the semiconductor substrate in the portion of the substrate between the two portions of conductive material. The diffusion barrier prevents any dopant from the conductive material from diffusing into the polycrystalline silicon material thereby allowing the polycrystalline silicon material to function as a load resistor having a high resistance in the giga-ohms range.

Self-Aligning Contact And Interconnect Structure

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US Patent:
54831040, Jan 9, 1996
Filed:
Sep 28, 1992
Appl. No.:
7/953410
Inventors:
Norman Godinho - Los Altos Hills CA
Tsu-Wei F. Lee - Monte Sereno CA
Richard F. Motta - Los Altos CA
Joseph Tzou - Belmont CA
Jai-Man Baik - San Jose CA
Assignee:
Paradigm Technology, Inc. - San Jose CA
International Classification:
H01L 2348
H01L 2702
US Classification:
257758
Abstract:
An MOS transistor for use in an integrated circuit is fabricated with a self-aligning contact and interconnect structure which allows for higher packing density. Self-aligning source and drain contacts overlap the gate but are prevented from a short circuiting to the gate by oxide insulation between the source/drain contacts and the gate, and a layer of silicon nitride above the gate. Contacts to the gate are made on top of the gate over the active region of the transistor because the source and drain regions are protected by a hardened layer of photoresist during etching of insulation to expose the gate contact. Source, drain and gate contacts are protected by a layer of titanium silicide so that interconnects are not required to completely cover these areas. Low resistance interconnects are formed of doped polysilicon covered by titanium silicide encapsulated by a thin film of titanium nitride.

Self-Aligning Contact And Interconnect Structure

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US Patent:
51667711, Nov 24, 1992
Filed:
Jan 12, 1990
Appl. No.:
7/464496
Inventors:
Norman Godinho - Los Altos Hills CA
Frank T. Lee - Monte Sereno CA
Richard F. Motta - Los Altos CA
Joseph Tzou - Belmont CA
Jai-man Baik - San Jose CA
Assignee:
Paradigm Technology, Inc. - San Jose CA
International Classification:
H01L 21283
H01L 2188
US Classification:
257368
Abstract:
An MOS transistor for use in an integrated circuit, particularly CMOS integrated circuits, is fabricated with a self-aligning contact and interconnect structure which allows for higher packing density. Self-aligning source and drain contacts overlap the gate but are prevented from short circuiting to the gate by oxide insulation between source/drain contacts and the gate, and a layer of silicon nitride above the gate. Contacts to the gate are made on top of the gate over the active region of the transistor because the source and drain regions are protected by a hardened layer of photoresist during etching of insulation to expose the gate contact. Source, drain and gate contacts are protected by a layer of titanium silicide so that interconnects are not required to completely cover these areas. Low resistance interconnects are formed of titanium silicide encapsulated by a thin film of titanium nitride.

Methods For Fabricating Integrated Circuits Including Openings To Transistor Regions

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US Patent:
56209193, Apr 15, 1997
Filed:
Mar 30, 1995
Appl. No.:
8/413976
Inventors:
Norman Godinho - Los Altos Hills CA
Frank T.W. Lee - Monte Sereno CA
Richard F. Motta - Los Altos CA
Joseph Tzou - Belmont CA
Jai-man Baik - San Jose CA
Assignee:
Paradigm Technology, Inc. - San Jose CA
International Classification:
H01L 218244
US Classification:
438230
Abstract:
An MOS transistor for use in an integrated circuit, particularly CMOS integrated circuits, is fabricated with a self-aligning contact and interconnect structure which allows for higher packing density. Self-aligning source and drain contacts overlap the gate but are prevented from short circuiting to the gate by oxide insulation between the source/drain contacts and the gate, and a layer of silicon nitride above the gate. Contacts to the gate are made on top of the gate over the active region of the transistor because the source and drain regions are protected by a hardened layer of photoresist during etching of insulation to expose the gate contact. Source, drain and gate contacts are protected by a layer of titanium silicide so that interconnects are not required to completely cover these areas. Low resistance interconnects are formed of titanium silicide encapulated by a thin film of titanium nitride.

Compact Sram Cell Layout

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US Patent:
51247747, Jun 23, 1992
Filed:
Jul 19, 1990
Appl. No.:
7/555559
Inventors:
Norman Godinho - Los Altos Hills CA
Tsu-Wei F. Lee - Monte Sereno CA
Richard F. Motta - Los Altos CA
Joseph Tzou - Belmont CA
Jai-Man Baik - San Jose CA
Assignee:
Paradigm Technology, Inc. - San Jose CA
International Classification:
H01L 2702
H01L 2348
G11C 1100
G11C 1134
US Classification:
357 41
Abstract:
A compact cell design for a static random access memory cell is achieved. The cell has two transistors with gates substantially parallel to each other. One interconnect connects the gate of one transistor to an electrode of the other transistor. Another interconnect connects the gate of the other transistor to an electrode of the first transistor. The two gates and the two interconnects form substantially a rectangle. A power supply circiut line is disposed outside the rectangle. This line and the two interconnects are formed from one conductive layer.

Method Of Fabricating A High Resistance Polysilicon Load Resistor

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US Patent:
51680769, Dec 1, 1992
Filed:
Jul 1, 1991
Appl. No.:
7/724008
Inventors:
Norman Godinho - Los Altos Hills CA
Frank T. Lee - Monte Sereno CA
Richard F. Motta - Los Altos CA
Joseph Tzou - Belmont CA
Jai-man Baik - San Jose CA
Assignee:
Paradigm Technology, Inc. - San Jose CA
International Classification:
H01L 2170
US Classification:
437 60
Abstract:
A load resistor for use in a semiconductor integrated circuit consists of two portions of conductive material, typically strips of either a silicide or a composite polycrystalline silicon layer and silicide layer formed thereon, formed on a semiconductor substrate and separated from each other by a selected distance. An electrically conductive dopant diffusion barrier is formed on the first and second portions of conductive material. A polycrystalline silicon material is then placed on the structure such that one portion of the polycrystalline silicon material is in ohmic contact through the diffusion barrier with the first portion of conductive material and the other portion of the polycrystalline silicon material is in ohmic contact through the diffusion barrier with the second portion of conductive material. Typically the polycrystalline silicon material is placed on an insulation layer formed on the semiconductor substrate in the portion of the substrate between the two portions of conductive material. The diffusion barrier prevents any dopant from the conductive material from diffusing into the polycrystalline silicon material thereby allowing the polycrystalline silicon material to function as a load resistor having a high resistance in the giga-ohms range.

Self-Aligning Contact And Interconnect Structure

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US Patent:
56568614, Aug 12, 1997
Filed:
May 25, 1995
Appl. No.:
8/450847
Inventors:
Norman Godinho - Los Altos Hills CA
Tsu-Wei Frank Lee - Monte Sereno CA
Richard F. Motta - Los Altos CA
Joseph Tzou - Belmont CA
Jai-Man Baik - San Jose CA
Assignee:
Paradigm Technology, Inc. - San Jose CA
International Classification:
H01L 2348
US Classification:
257758
Abstract:
An MOS transistor for use in an integrated circuit is fabricated with a self-aligning contact and interconnect structure which allows for higher packing density. Self-aligning source and drain contacts overlap the gate but are prevented from a short circuiting to the gate by oxide insulation between the source/drain contacts and the gate, and a layer of silicon nitride above the gate. Contacts to the gate are made on top of the gate over the active region of the transistor because the source and drain regions are protected by a hardened layer of photoresist during etching of insulation to expose the gate contact. Source, drain and gate contacts are protected by a layer of titanium silicide so that interconnects are not required to completely cover these areas. Low resistance interconnects are formed of doped polysilicon covered by titanium silicide encapsulated by a thin film of titanium nitride.

Oxynitride Fuse Protective/Passivation Film For Integrated Circuit Having Resistors

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US Patent:
53651049, Nov 15, 1994
Filed:
Mar 25, 1993
Appl. No.:
8/036754
Inventors:
Norman Godinho - Los Altos Hills CA
Assignee:
Paradigm Technology, Inc. - San Jose CA
International Classification:
H01L 2702
US Classification:
257529
Abstract:
An oxynitride passivation layer and/or fuse protective layer for an SRAM cell having load resistors, where the composition of the oxynitride layer minimizes the effect of hydrogen diffusion on the resistance of underlying load resistors. The index of refraction of the oxynitride is between 1. 60 and 1. 85. This oxynitride does not substantially diffuse hydrogen into the load resistors even when heated to temperatures over 400. degree. C. , and hence, avoids altering resistance during subsequent annealing steps.
Norman Te Godinho from Los Altos Hills, CA, age ~84 Get Report