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Nazanin D Darbanian

from Rancho Santa Fe, CA
Age ~46
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Also known as:
Nazanin Farahani Darbanian, Nozanin Darbanian, Nazanin Farahani, N N
Related to:
Karim DarbanianArash Farahani, 44Farahani Shahin, 49
Connected to:
Cindi E Darbe, 45Don D Darbeau, 44Starletta K Darbeau, 67Caroline A Darbee, 46Kristin Darbee, 51Mary J Darbee, 66Russell E Darbee, 74Sarah M Darbee, 37Stacey J Darbee, 45Nicolas R Darbel, 60

Nazanin Darbanian Phones & Addresses

  • Rancho Santa Fe, CA
  • 13566 Chamise Vista Ln, San Diego, CA 92130
  • La Jolla, CA
  • 9047 Blanche Dr, Scottsdale, AZ 85260 (480) 699-2795
  • 9711 Jagged Peak Rd, Scottsdale, AZ 85262 (480) 699-2795
  • Chandler, AZ

Work

Company: Max reliance Jun 2009 Position: Ceo

Education

Degree: PhD School / High School: Arizona State University 2005 to 2010 Specialities: Electrical Engineering

Industries

Semiconductors

Resumes

Resumes

Nazanin Darbanian Photo 1

Senior Staff Engineer

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Location:
San Diego, CA
Industry:
Semiconductors
Work:
Max Reliance since Jun 2009
CEO
ON Semiconductor Jan 2008 - Jun 2009
Principal Engineer (Office of CTO)
Freescale Semiconductor Jun 2003 - Jan 2008
RF/Analog Design Engineer
Arizona State University Jan 2002 - May 2003
Research Associate
Education:
Arizona State University 2005 - 2010
PhD, Electrical Engineering Arizona State University 2002 - 2004
M.S.c, Electrical Engineering University of Tehran 1996 - 2001
B.Sc., Electrical Engineering

Business Records

Name / Title
Company / Classification
Phones & Addresses
Nazanin Darbanian
President
MAX RELIANCE
Mfg Semiconductors/Related Devices
PO Box 910797, San Diego, CA 92191

Publications

Us Patents

Compressed Vector-Based Spectral Analysis Method And System For Nonlinear Rf Blocks

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US Patent:
20060052988, Mar 9, 2006
Filed:
Nov 21, 2003
Appl. No.:
10/535616
Inventors:
Shahin Farahani - Chandler AZ, US
Sayfe Kiaei - Scottsdale AZ, US
Nazanin Darbanian - Chandler AZ, US
International Classification:
G06F 17/10
US Classification:
703002000
Abstract:
A method and system of simulating components using a compressed signal representation. In some embodiments compressed vector based equivalent signals and blocks are used to model signal processing systems, in particular RF wireless components.

Efficient Non-Iterative Frequency Domain Method And System For Nonlinear Analysis

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US Patent:
20070033000, Feb 8, 2007
Filed:
Jul 19, 2006
Appl. No.:
11/489102
Inventors:
Shahin Farahani - Scottsdale AZ, US
Sayfe Kiaei - Tempe AZ, US
Nazanin Darbanian - Scottsdale AZ, US
International Classification:
G06F 9/455
US Classification:
703028000
Abstract:
A non-iterative frequency domain method for the accurate and efficient simulation of nonlinear systems is presented. In one aspect of the present invention, simulating a nonlinear system is accomplished by first modeling the system and generating parameters that describe the nonlinear system. The system is represented in the frequency domain as an inverse convolution equation (ICE), comprising cascaded convolutions and frequency representations of known and unknown signals. Next, the order of the ICE is determined based upon the degree of nonlinearity in the system. Finally, a general ICE solver algorithm is adapted to the ICE order of the frequency model, and the specific ICE solver algorithm is applied to in order to solve for an unknown signal. In another aspect of the invention, the non-iterative method for simulating nonlinear systems is combined with cross-referenced coordinate (CRC) techniques in order to increase the computational efficiency of the simulation.

Differential Threshold Voltage Non-Volatile Memory And Related Methods

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US Patent:
20110261634, Oct 27, 2011
Filed:
Apr 8, 2011
Appl. No.:
13/083405
Inventors:
Sameer M. Venugopal - Chandler AZ, US
David R. Allee - Phoenix AZ, US
Lawrence T. Clark - Phoenix AZ, US
Nazanin Darbanian - San Diego CA, US
Assignee:
Arizona Board of Regents, for and on behalf of Arizona State University - Scottsdale AZ
International Classification:
G11C 7/00
H05K 13/00
US Classification:
36518915, 365189011, 29825, 365203
Abstract:
Embodiments and examples of differential threshold voltage non-volatile memories and related methods are described herein. Other embodiments, examples thereof, and related methods are also disclosed herein.

Capacitively-Coupled Hybrid Parallel Power Supply

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US Patent:
20160216723, Jul 28, 2016
Filed:
Jan 27, 2015
Appl. No.:
14/606753
Inventors:
- San Diego CA, US
James Thomas Doyle - Carlsbad CA, US
Nazanin Darbanian - San Diego CA, US
Shree Krishna Pandey - San Diego CA, US
Yi Cao - San Diego CA, US
International Classification:
G05F 3/08
Abstract:
Operational mode changes in a system-on-a-chip (SoC) integrated circuit in a complex device such as a mobile phone cause spikes in current demand which can cause voltage droops that disrupt operation of the SoC. A hybrid parallel power supply capacitively couples a switching-mode power supply and a low-dropout voltage regulator in parallel to provide high efficiency and fast response times. The low-dropout voltage regulator may include a class-AB operational transconductance amplifier driving the coupling capacitor. The switching-mode power supply and the low-dropout voltage regulator can regulate their outputs to slightly difference voltage levels. This can allow the switching-mode power supply to supply most of the SoC's current demands.

Hybrid Parallel Regulator And Power Supply Combination For Improved Efficiency And Droop Response With Direct Current Driven Output Stage Attached Directly To The Load

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US Patent:
20160179181, Jun 23, 2016
Filed:
Dec 22, 2014
Appl. No.:
14/579899
Inventors:
- San Diego CA, US
Zhengming Fu - San Diego CA, US
Farsheed Mahmoudi - San Diego CA, US
Amirali Shayan Arani - San Diego CA, US
Nazanin Darbanian - San Diego CA, US
International Classification:
G06F 1/32
Abstract:
Operational mode changes in a system-on-a-chip (SoC) integrated circuit in a complex device such as a mobile phone cause spikes in current demand which can cause voltage droops that disrupt operation of the SoC. A hybrid parallel power supply connects a switching-mode power supply and a low-dropout voltage regulator in parallel to provide high efficiency and fast response times. Integration of the voltage regulator on the SoC reduces parasitic impedance be between the voltage regulator and the load to aid in reducing voltage droops. The switching-mode power supply and the low-dropout voltage regulator can regulate their outputs to slightly difference voltage levels. This can allow the switching-mode power supply to supply most of the SoC's current demands.

Multilayer Ceramic Capacitor

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US Patent:
20150310990, Oct 29, 2015
Filed:
Apr 24, 2014
Appl. No.:
14/261373
Inventors:
- San Diego CA, US
Shree Krishna Pandey - San Diego CA, US
Nazanin Darbanian - San Diego CA, US
John David Eaton - San Diego CA, US
Assignee:
QUALCOMM INCORPORATED - San Diego CA
International Classification:
H01G 4/30
Abstract:
Aspects of a method of manufacturing a capacitor are provided. The method includes layering a plurality of dielectric plates. The plurality of dielectric plates includes a first dielectric plate having a first conductive region and a second conductive region on a surface of the first dielectric plate. The method further includes forming an inner electrode through an axis of the layered plurality of dielectric plates. The inner electrode electrically couples to the first conductive region on the surface of the first dielectric plate. The method further includes forming an outer electrode, where the outer electrode electrically couples to the second conductive region on the surface of the first dielectric plate.

Capacitor With Low Equivalent Series Inductance

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US Patent:
20150255216, Sep 10, 2015
Filed:
Mar 7, 2014
Appl. No.:
14/201469
Inventors:
- San Diego CA, US
Shree Krishna Pandey - San Diego CA, US
Irfan Khan - San Diego CA, US
Nazanin Darbanian - San Diego CA, US
John David Eaton - San Diego CA, US
Assignee:
QUALCOMM INCORPORATED - San Diego CA
International Classification:
H01G 4/30
H05K 1/18
H01L 49/02
Abstract:
A capacitor with low equivalent series inductance includes multiple electrode layers arranged in parallel with alternating ones of the electrode layers connected together to form the two electrodes of the capacitor. A first set of the electrode layers are connected by an outer wall. A second set of the electrode layers are connected by a central post. Terminals on the capacitor can be spaced on a surface so that signals can be conveniently routed when the capacitor is mounted on or in a printed circuit board or integrated circuit package. Terminals can be included on opposing surfaces of the capacitors to provide for stacking. Additionally, one of the terminals substantially surrounds the other terminal and can provide electromagnetic shielding.
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Nazanin D Darbanian from Rancho Santa Fe, CA, age ~46 Get Report