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Naushad K Variam

from Marblehead, MA
Age ~63
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Also known as:
Naushad F Variam, Naushad M, A Naushad Variam
Phone and address:
19 Saturn Rd, Marblehead, MA 01945
(781) 639-9835
Related to:
Jasmine Variam, 25
Connected to:
Basil B Varian, 91Benjamin M Varian, 33Brandie T Varian, 36Bullard Varian, 37Leslie D Varian, 64Lisa Varian, 57Nigel S Varian, 78Tahleen Varian, 45Bruce F Variano, 66Michael Variano, 66

Naushad Variam Phones & Addresses

  • 19 Saturn Rd, Marblehead, MA 01945 (781) 639-9835 (781) 724-0467
  • 8495 Cashmur Ln, Portland, OR 97225
  • Bronx, NY
  • Bulverde, TX
  • Richland, WA
  • Gloucester, MA
  • Lafayette, IN
  • 19 Saturn Rd, Marblehead, MA 01945 (781) 724-0467

Work

Company: Applied materials Jun 2013 Position: Senior director, technology

Education

Degree: Doctorates, Doctor of Philosophy School / High School: University of Washington 1985 to 1991 Specialities: Chemical Engineering

Skills

Technology • Semiconductors • Varian

Industries

Semiconductors

Resumes

Resumes

Naushad Variam Photo 1

Senior Director, Technology

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Location:
19 Saturn Rd, Marblehead, MA 01945
Industry:
Semiconductors
Work:
Applied Materials
Senior Director, Technology
Varian Semiconductor 2010 - 2013
Director, New Product Marketing and Applications
Varian Semiconductor 2005 - 2010
Senior Manager
Pacific Northwest National Laboratory Sep 1994 - Mar 1996
Post Doctoral Scientist
Education:
University of Washington 1985 - 1991
Doctorates, Doctor of Philosophy, Chemical Engineering Indian Institute of Technology, Madras 1980 - 1985
Skills:
Technology
Semiconductors
Varian

Publications

Us Patents

Plasma Implantation Of Deuterium For Passivation Of Semiconductor-Device Interfaces

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US Patent:
7378335, May 27, 2008
Filed:
Nov 29, 2005
Appl. No.:
11/288828
Inventors:
Steven R. Walther - Andover MA, US
Ukyo Jeong - Eugene OR, US
Sandeep Mehta - Boxford MA, US
Naushad K. Variam - Marblehead MA, US
Assignee:
Varian Semiconductor Equipment Associates, Inc. - Gloucester MA
International Classification:
H01L 21/425
US Classification:
438528, 257E21334
Abstract:
A method for fabricating a semiconductor-based device includes providing a substrate including a semiconductor layer, forming a gate dielectric layer on the semiconductor layer, forming a plasma including deuterium, plasma implanting deuterium from the plasma into the substrate, and annealing the substrate to promote passivation of the interface between the dielectric layer and the semiconductor layer.

In Situ Surface Contamination Removal For Ion Implanting

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US Patent:
7544959, Jun 9, 2009
Filed:
Apr 8, 2008
Appl. No.:
12/099420
Inventors:
Steven R. Walther - Andover MA, US
Sandeep Mehta - Boxford MA, US
Naushad Variam - Marblehead MA, US
Ukyo Jeong - Andover MA, US
Assignee:
Varian Semiconductor Equipment Associates, Inc. - Gloucester MA
International Classification:
H01J 37/317
H01J 37/36
H01L 21/302
US Classification:
25049221, 2504922, 118723 R, 216 58
Abstract:
Methods and apparatus that introduce, within the ion implant chamber or an isolated chamber in communication therewith, the capability to remove contaminants and oxide surface layers on a wafer surface prior to ion implantation, are disclosed. The mechanisms for removal of contaminants include conducting: a low energy plasma etch, heating the wafer and application of ultraviolet illumination, either in combination or individually. As a result, implantation can occur immediately after the cleaning/preparation process without the contamination potential of exposure of the wafer to an external environment. The preparation allows for the removal of surface contaminants, such as water vapor, organic materials and surface oxides.

In Situ Surface Contaminant Removal For Ion Implanting

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US Patent:
20060040499, Feb 23, 2006
Filed:
Aug 20, 2004
Appl. No.:
10/922710
Inventors:
Steve Walther - Andover MA, US
Sandeep Mehta - Boxford MA, US
Naushad Variam - Marblehead MA, US
Ukyo Jeong - Andover MA, US
International Classification:
H01L 21/302
C23F 1/00
C03C 25/68
US Classification:
438689000, 315111810, 11872300R, 156345100, 216058000
Abstract:
Methods and apparatus that introduce, within the ion implant chamber or an isolated chamber in communication therewith, the capability to remove contaminants and oxide surface layers on a wafer surface prior to ion implantation, are disclosed. The mechanisms for removal of contaminants include conducting: a low energy plasma etch, heating the wafer and application of ultraviolet illumination, either in combination or individually. As a result, implantation can occur immediately after the cleaning/preparation process without the contamination potential of exposure of the wafer to an external environment. The preparation allows for the removal of surface contaminants, such as water vapor, organic materials and surface oxides.

Shallow-Junction Fabrication In Semiconductor Devices Via Plasma Implantation And Deposition

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US Patent:
20060205192, Sep 14, 2006
Filed:
Mar 9, 2005
Appl. No.:
11/076695
Inventors:
Steven Walther - Andover MA, US
Sandeep Mehta - Beverly MA, US
Ukyo Jeong - Andover MA, US
Naushad Variam - Marblehead MA, US
Assignee:
Varian Semiconductor Equipment Associates, Inc. - Gloucester MA
International Classification:
H01L 21/425
US Classification:
438513000, 438514000, 438528000
Abstract:
A method for fabricating a semiconductor-based device includes disposing a substrate in a process chamber of a process tool, plasma implanting a dopant species from a plasma into a portion of the substrate in the process chamber, and plasma depositing a diffusion barrier on the implanted portion of the substrate prior to removing the at least one substrate from the process tool. The diffusion barrier can be deposited in the same chamber as that used for dopant implantation or a different chamber of the process tool.

Plasma Ion Implantation Systems And Methods Using Solid Source Of Dopant Material

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US Patent:
20060219952, Oct 5, 2006
Filed:
Mar 9, 2005
Appl. No.:
11/076696
Inventors:
Sandeep Mehta - Beverly MA, US
Steven Walther - Andover MA, US
Naushad Variam - Marblehead MA, US
Assignee:
Varian Semiconductor Equipment Associates, Inc. - Gloucester MA
International Classification:
H01J 37/08
G21K 5/10
US Classification:
250492210
Abstract:
Plasma ion implantation apparatus includes a process chamber, a platen located in the process chamber for supporting a substrate, a dopant source including a solid dopant element and a vaporizer to vaporize dopant material from the solid dopant element, a plasma source to produce a plasma containing ions of the dopant material, and an implant pulse source to apply implant pulses to the platen for accelerating the ions of the dopant material from the plasma into the substrate.

Metal Work Function Adjustment By Ion Implantation

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US Patent:
20070048984, Mar 1, 2007
Filed:
Aug 31, 2005
Appl. No.:
11/217699
Inventors:
Steven Walther - Andover MA, US
Ukyo Jeong - Andover MA, US
Sandeep Mehta - Boxford MA, US
Naushad Variam - Marblehead MA, US
International Classification:
H01L 21/425
US Classification:
438533000
Abstract:
A system, method and program product for adjusting metal work function by ion implantation is disclosed. The invention determines the work function of the metal and determines a desired work function threshold for the metal. The desired work function threshold may be a range and is usually based on the work function of the substrate. An ion implanter system is then used to implant ions to at least a portion of the metal. The ion implantation is usually a high-energy ion stream including a material that is calculated to modify the work function of the metal. The ion implanter system continues to transmit the ion stream into the metal until the work function of the metal meets the desired work function threshold.

Methods And Apparatus For Plasma Implantation With Improved Dopant Profile

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US Patent:
20070069157, Mar 29, 2007
Filed:
Sep 28, 2005
Appl. No.:
11/237385
Inventors:
Sandeep Mehta - Beverly MA, US
Steven Walther - Andover MA, US
Naushad Variam - Marblehead MA, US
Ukyo Jeong - Eugene OR, US
Assignee:
Varian Semiconductor Equipment Associates, Inc. - Gloucester MA
International Classification:
H01J 37/08
US Classification:
250492210
Abstract:
Methods and apparatus for plasma ion implantation with improved dopant profiles are provided. A plasma ion implantation system includes a process chamber, a plasma source to generate a plasma in the process chamber, a platen to hold the substrate in the process chamber and a pulse source to generate implant pulses to accelerate ions from the plasma into the substrate. In one aspect, the pulse source generates implant pulses having pulse widths that are sufficiently long to limit plasma ion implantation during a transient period at the start of each implant pulse to a small fraction of the total implanted dose. In another aspect, ions are generated in a region of the process chamber near a reference potential, such as ground, and are accelerated from the region of plasma generation to the platen. Plasma generation may be enabled after the start of each implant pulse and may be disabled before the end of each implant pulse.

Wordline Contact Formation In Nand Devices

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US Patent:
20220352182, Nov 3, 2022
Filed:
May 3, 2021
Appl. No.:
17/306047
Inventors:
- Santa Clara CA, US
Tristan Y. Ma - Lexington MA, US
Johannes M. van Meer - Middleton MA, US
John Hautala - Beverly MA, US
Naushad K. Variam - Marblehead MA, US
Assignee:
Applied Materials, Inc. - Santa Clara CA
International Classification:
H01L 27/1157
H01L 27/11524
H01L 27/11551
H01L 27/11578
G11C 8/14
Abstract:
Disclosed are approaches for 3D NAND structure fabrication. One method may include providing a stack of layers comprising a first and second plurality of layers, and forming a plurality of trenches in the stack of layers, wherein each of the trenches includes a tiered sidewall. A first trench may be formed to a first depth, and a second trench may be formed to a second depth, which is greater than the first depth. The method may further include forming a liner within the trenches, wherein the liner is deposited at a non-zero angle of inclination relative to a normal extending perpendicular from the top surface of the stack of layers. The liner may have a first thickness along the tiered sidewall of the first trench and a second thickness along the tiered sidewall of the second trench, wherein the first thickness is greater than the second thickness.
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Naushad K Variam from Marblehead, MA, age ~63 Get Report